CH5001A-L ETC1 [List of Unclassifed Manufacturers], CH5001A-L Datasheet - Page 23

• Manufacturer Part Number: CH5001A-L
• Description: CMOS COLOR DIGITAL VIDEO CAMERA
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

CHRONTEL
Vertical Start Register
Register VS determines the number of lines between the leading edge of V Sync and the first active line to be output
on the Y[7:0] and C[7:0] pins. The number is in units of lines; the range is 0 to 31 lines. When ELFA = 1, this
register is ignored, and there is always a one line delay between the leading edge of vertical sync and the first line
with active video.
The YDEL (bit 6) controls the delay in the luma processing path. The value should match the setting of CHL.
Electronic Shutter Length High Byte
The ESLH register, combined with the ESLE and ESLL registers determine the length of the electronic shutter.
Electronic Shutter Length Low Byte
Registers ESLE, ESLH and ESLL specify the duration of the electronic shutter. These 21 bits are concatenated into
a single 21-bit word ({ESLE,ESLH,ESLL}) whose value is multiplied by 8. The shutter is enabled for this number
of MCLKs. The duration of the shutter can, therefore, be determined from the equation (8*(65536*ESLE +
256*ESLH + ESLL))/MCLK. The range is from 0mS to 699mS, but is limited to a lower value in some frame rates
(see Frame Rate Register description). When the autoshutter algorithm is controlling the shutter value and this
register is read out, the autoshutter generated value is read instead of the actual IIC register content.
201-0000-032 Rev 3.0, 6/2/99
BIT:
SYMBOL:
TYPE:
DEFAULT:
BIT:
SYMBOL:
TYPE:
DEFAULT:
BIT:
SYMBOL:
TYPE:
DEFAULT:
ESLH7
ESLL7
R/W
R/W
7
7
1
7
0
ESLH6
ESLL6
YDEL
R/W
R/W
R/W
6
0
6
1
6
0
ESLH5
ESLL5
R/W
R/W
5
5
1
5
0
ESLH4
ESLL4
R/W
R/W
R/W
VS4
4
1
4
1
4
0
ESLH3
ESLL3
VS3
R/W
R/W
R/W
3
0
3
0
3
0
ESLH2
ESLL2
VS2
R/W
R/W
R/W
2
1
2
0
2
0
Symbol:VS
Address:03h
Bits:6
Symbol:ESLH
Address:04h
Bits:8
Symbol:ESLL
Address:05h
Bits:8
ESLH1
ESLL1
R/W
R/W
R/W
VS1
1
0
1
0
1
0
CH5001A
ESLH0
ESLL0
R/W
R/W
R/W
VS0
0
1
0
0
0
0
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