AT26DF081A-SSU-RET Atmel, AT26DF081A-SSU-RET Datasheet
AT26DF081A-SSU-RET
Related parts for AT26DF081A-SSU-RET
AT26DF081A-SSU-RET Summary of contents
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... Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-lead SOIC (150-mil and 200-mil wide) 1. Description The AT26DF081A is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer-based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The ...
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... Specifically designed for use in 3-volt systems, the AT26DF081A supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing. ...
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Pin Descriptions and Pinouts Table 2-1. Pin Descriptions Symbol Name and Function CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode ...
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... WP 4. Memory Array To provide the greatest flexibility, the memory array of the AT26DF081A can be erased in four levels of granularity including a full chip erase. In addition, the array has been divided into phys- ical sectors of various sizes, of which each sector can be individually protected from program and erase operations ...
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Figure 4-1. Memory Architecture Diagram Internal Sectoring for 64KB Sector Protection Block Erase Function (D8h Command) (52h Command) (20h Command) 32KB (Sector 18) 64KB 8KB (Sector 17) 8KB (Sector 16) 16KB (Sector 15) 64KB 64KB (Sector 14) 64KB 64KB (Sector ...
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... Device Operation The AT26DF081A is controlled by a set of instructions that are sent from a host controller, com- monly referred to as the SPI Master. The SPI Master communicates with the AT26DF081A via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO) ...
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Table 6-1. Command Listing Command Read Commands Read Array Read Array (Low Frequency) Program and Erase Commands Block Erase (4 Kbytes) Block Erase (32 Kbytes) Block Erase (64 Kbytes) Chip Erase Byte/Page Program (1 to 256 Bytes) Sequential Program Mode ...
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... The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 7-1. Read Array – 0Bh Opcode SCK OPCODE MSB HIGH-IMPEDANCE SO AT26DF081A ADDRESS BITS A23- ...
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Figure 7-2. Read Array – 03h Opcode CS SCK Program and Erase Commands 8.1 Byte/Page Program The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of data to be programmed into ...
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... SCK MSB HIGH-IMPEDANCE SO Figure 8-2. Page Program SCK OPCODE MSB HIGH-IMPEDANCE SO AT26DF081A 10 time to determine if the data bytes have finished programming OPCODE ADDRESS BITS A23- ...
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Sequential Program Mode The Sequential Program Mode improves throughput over the Byte/Page Program command when the Byte/Page Program command is used to program single bytes only into consecutive address locations. For example, some systems may be designed to program ...
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... Sequential Program Mode – Waiting Maximum Byte Program Time CS Seqeuntial Program Mode Command SI Opcode A A 23-16 15-8 First Address to Program HIGH-IMPEDANCE SO Note: Each transition AT26DF081A 12 Status Register Read Seqeuntial Program Mode Command Command 05h Opcode Data STATUS REGISTER DATA t BP Seqeuntial Program Mode ...
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Block Erase A block Kbytes can be erased (all bits set to the logical “1” state single oper- ation by using one of three different opcodes for the Block Erase command. An ...
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... WEL bit in the Status Register will be reset back to the logical “0” state. The device also incorporates an intelligent erasing algorithm that can detect when a byte loca- tion fails to erase properly erase error occurs, it will be indicated by the EPE bit in the Status Register. AT26DF081A 14 Block Erase CS 0 ...
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Figure 8-6. 9. Protection Commands and Features 9.1 Write Enable The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Regis- ter to a logical “1” state. The WEL bit must be set ...
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... Any additional data clocked into the device will be ignored. When the CS pin is deas- serted, the Sector Protection Register corresponding to the physical sector addressed by A23 - A0 will be set to the logical “1” state, and the sector itself will then be protected from AT26DF081A 16 Write Disable ...
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In addition, the WEL bit in the Status Register will be reset back to the logical “0” state. The complete three address bytes must be clocked into the device before the CS pin is deas- serted, ...
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... Status Register. Conversely, to per- form a Global Unprotect, the same WP and SPRL conditions must be met but the system must write a logical “0” to bits and 2 of the Status Register. necessary for a Global Protect or Global Unprotect to be performed. AT26DF081A 18 Unprotect Sector CS ...
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Table 9-2. WP State Essentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector Protection Registers are not locked), then writing a 00h to the Status Register will perform a ...
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... In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bit in the Status Register can be read to determine if all, some, or none of the sectors are software protected (refer to the AT26DF081A 20 for details on the Status Register format and what values can be Read Sector Protection Register – Output Data Sector Protection Register Value Sector Protection Register value is 0 (sector is unprotected) ...
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Figure 9-5. CS SCK SI SO 9.7 Protected States and the Write Protect (WP) Pin The WP pin is not linked to the memory array itself and has no direct effect on the protection sta- tus of the memory array. ...
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... Tables 9-4 and 9-5 Table 9-4. (Don't Care) Note: Table 9- AT26DF081A 22 detail the various protection and locking states of the device. Sector Protection Register States Sector Protection Register “n” represents a sector number Hardware and Software Locking SPRL Locking SPRL Change Allowed ...
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Status Register Commands 10.1 Read Status Register The Status Register can be read to determine the device's ready/busy status, as well as the sta- tus of many other functions such as Hardware Locking and Software Protection. The Status Register ...
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... Protect Sector command or the Global Protect feature. If the SWP bits indicate that some of the sectors have been protected, then the individual Sector Pro- tection Registers can be read with the Read Sector Protection Registers command to determine which sectors are in fact protected. AT26DF081A 24 3600G–DFLASH–06/09 ...
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WEL Bit The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0” state, the device will not accept any program, erase, Protect Sector, Unprotect Sector, or Write ...
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... WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP pin must be deasserted. Table 10-2. Bit 7 SPRL Figure 10-2. Write Status Register AT26DF081A 26 page 18 for more details. Write Status Register Format Bit 6 ...
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... Product Version Code Hex Bit 0 Value Details 1Fh JEDEC Code: 0001 1111 (1Fh for Atmel) 1 Family Code: 010 (AT26DFxxx series) 45h Density Code: 00101 (8-Mbit) 1 MLC Code: 000 (1-bit/cell technology) 01h Product Version:00001 (First major revision) 1 Value 1Fh ...
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... The Deep Power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. The Deep Power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the Deep Power-down mode. AT26DF081A ...
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Figure 11-2. Deep Power-down 11.3 Resume from Deep Power-down In order exit the Deep Power-down mode and resume normal device operation, the Resume from Deep Power-down command must be issued. The Resume from Deep Power-down com- mand is the only ...
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... If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state. Figure 11-4. Hold Mode CS SCK HOLD AT26DF081A 30 Hold Hold Hold 3600G–DFLASH–06/09 ...
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... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT26DF081A -40⋅C to 85⋅C 2.7V to 3.6V Min Typ Max 25 ...
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... Chip Select High to Standby Mode RDPD Notes: 1. Not 100% tested (value guaranteed by design and characterization load at 70 MHz load at 66 MHz. 3. Only applicable as a constraint for the Write Status Register command when SPRL = 1 AT26DF081A 32 Min Max Units 70 MHz 33 MHz 6 ...
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Program and Erase Characteristics Symbol Parameter (1) t Page Program Time (256 Bytes Byte Program Time BP (1) t Block Erase Time BLKE (2) t Chip Erase Time CHPE (2) t Write Status Register Time WRSR Notes: ...
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... Figure 13-1. Serial Input Timing CS t CSLS SCK MSB HIGH-IMPEDANCE SO Figure 13-2. Serial Output Timing CS SCK Figure 13-3. HOLD Timing – Serial Input CS SCK HOLD SI HIGH-IMPEDANCE SO AT26DF081A 34 t CSLH t t SCKH SCKL t DH LSB HHH HLS t HLH t CSH t ...
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Figure 13-4. HOLD Timing – Serial Output CS SCK t HHH HOLD SI SO Figure 13-5. WP Timing for Write Status Register Command When SPRL = WPS WP SCK SI 0 MSB OF WRITE STATUS REGISTER OPCODE ...
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... SCK AT26DF081A-SSU 70 AT26DF081A-SU 8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.209” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) AT26DF081A 36 Package 8S1 8S2 Package Type Operation Range Industrial (-40⋅C to 85⋅C) ...
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Packaging Information 15.1 8S1 – JEDEC SOIC TOP VIEW e e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. ...
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... Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com AT26DF081A TOP VIEW ...
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Revision History Revision Level – Release Date History A – November 2005 Initial Release Added Global Protect and Global Unprotect Feature B – March 2006 Removed EPE bit from Status Register C – April 2006 Changed Note 5 of ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...