AT26DF081A-SSU-RET Atmel, AT26DF081A-SSU-RET Datasheet - Page 4

• Manufacturer Part Number: AT26DF081A-SSU-RET
• Manufacturer: Atmel

3. Block Diagram
4. Memory Array
4
SCK
WP
AT26DF081A
SO
CS
SI
INTERFACE
CONTROL
To provide the greatest flexibility, the memory array of the AT26DF081A can be erased in four
levels of granularity including a full chip erase. In addition, the array has been divided into phys-
ical sectors of various sizes, of which each sector can be individually protected from program
and erase operations. The sizes of the physical sectors are optimized for both code and data
storage applications, allowing both code and data segments to reside in their own isolated
regions.
down of each physical sector.
LOGIC
Figure 2-1.
AND
Figure 4-1 on page 5
GND
WP
SO
CS
8-SOIC Top View
1
2
3
4
PROTECTION LOGIC
CONTROL AND
8
7
6
5
illustrates the breakdown of each erase level as well as the break-
VCC
HOLD
SCK
SI
Y-DECODER
X-DECODER
AND LATCHES
I/O BUFFERS
Y-GATING
MEMORY
ARRAY
FLASH
DATA BUFFER
SRAM
3600G–DFLASH–06/09