AM186CC-50KC\W C AMD, AM186CC-50KC\W C Datasheet - Page 56

• Manufacturer Part Number: AM186CC-50KC\W C
• Manufacturer: AMD

56
USB Timing (Clocks)
USB Timing (Data/Jitter)
DCE
PCM (Slave)
Table 10. Numerical Key to Switching Parameter Symbols (Continued)
402
403
404
No.
98
10
11
12
13
14
15
16
17
18
1
2
3
4
5
1
2
3
4
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
1
Parameter
t
Am186™CC Communications Controller Data Sheet
Symbol
t
TCLKPER
t
t
t
t
t
t
t
t
t
DSHDIW
t
t
TCLKSU
TCLKHD
t
t
t
t
UCHCK
t
t
CHRAS
CHCAS
UCLCK
UCKHL
UCKLH
t
SYNSS
TCLKH
TCLKO
TCLKR
t
t
UCKIN
TCLKL
t
t
WSYN
t
COLV
t
SUFC
SUDC
t
CLKP
t
t
t
DCLT
t
t
t
t
t
DCD
HCD
t
DTW
HCF
DCT
DZF
DZF
DFT
DTZ
JR1
JR2
WH
WL
HFI
t
t
R
F
Description
DS High to data invalid—write
Column address valid delay
Change in RAS delay
Change in CAS delay
USBX1 period
USBX1 Low time
USBX1 High time
USBX1 fall time
USBX1 rise time
Rise time
Fall time
Consecutive transition jitter
Paired transition jitter
DCE clock period
DCE clock High
DCE clock Low
DCE clock to output delay
DCE clock setup
DCE clock hold
DCE clock rise/fall
PCM clock period
PCM clock High
PCM clock Low
Hold time from CLK Low to FSC valid
Delay time to valid TXD from CLK
Delay time to valid TXD from FSC
Setup time for FSC High to CLK Low
Delay time from CLK High to TXD valid
Setup time from RXD valid to CLK
Hold time from CLK Low to RXD invalid
Delay to TSC valid from CLK
Delay to TSC valid from FSC
Delay from CLK Low of last bit to TSC invalid
Hold time from CLK Low to FSC invalid
Time between successive synchronization pulses
FSC width invalid
Delay from last bit CLK Low to TXD weak drive
Delay from last bit CLK (plus one) High to TXD disable