AM186CC-50KD\W C AMD (ADVANCED MICRO DEVICES), AM186CC-50KD\W C Datasheet
AM186CC-50KD\W C
Specifications of AM186CC-50KD\W C
Related parts for AM186CC-50KD\W C
AM186CC-50KD\W C Summary of contents
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... Three programmable 16-bit timers – Hardware watchdog timer GENERAL DESCRIPTION ™ controller is the first member in the AMD Comm86™ product family. The Am186CC controller is a cost- effective, high-performance microcontroller solution for communications applications. This highly integrated microcontroller enables customers to save system microcontrollers and other 16-bit microcontrollers ...
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... Am186CC–25 KI\W Am186CC–40 2 Am186™CC Communications Controller Data Sheet C \W LEAD FORMING \W=Trimmed and Formed TEMPERATURE RANGE C= Am186CC Commercial ( Am186CC Industrial (T where case temperature C where ambient temperature A PACKAGE TYPE K=160-Pin Plastic Quad Flat Pack (PQFP) SPEED OPTION – MHz – ...
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TABLE OF CONTENTS Distinctive Characteristics ............................................................................................................ 1 General Description ..................................................................................................................... 1 Ordering Information .................................................................................................................... 2 Logic Diagram by Interface .......................................................................................................... 6 Logic Diagram by Default Pin Function ....................................................................................... 7 Pin Connection Diagram—160-Pin PQFP Package .................................................................... 8 Pin and Signal Tables ...
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... Index ................................................................................................................................... Index-1 LIST OF FIGURES Figure 1. Am186CC Controller Block Diagram ..................................................................... 28 Figure 2. Two-Component Address Example ...................................................................... 30 Figure 3. Am186CC Controller Address Bus — Default Operation ...................................... 35 Figure 4. Am186CC Controller—Address Bus Disable In Effect .......................................... 36 Figure 5. ISDN Terminal Adapter System Application ......................................................... 38 Figure 6. ISDN to Ethernet Low-End Router System Application ........................................ 38 Figure 7 ...
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Figure 31. PCM Highway Waveforms (Timing Slave) ............................................................ 75 Figure 32. PCM Highway Waveforms (Timing Master) .......................................................... 76 Figure 33. DCE Transmit Waveforms .................................................................................... 77 Figure 34. DCE Receive Waveforms ..................................................................................... 77 Figure 35. USB Data Signal Rise and Fall ...
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LOGIC DIAGRAM BY INTERFACE CLKOUT Reset/ RES Clocks RESOUT X1 X2 Address and A19–A0 20 Address/Data AD15–AD0 16 Buses ALE ARDY BHE BSIZE8 DEN DS 2 DRQ1–DRQ0 / DT/R Bus Status and HLDA Control HOLD RD 3 S2– ...
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LOGIC DIAGRAM BY DEFAULT PIN FUNCTION CLKOUT Reset/ RES Clocks RESOUT X1 X2 Address and A19–A0 20 Address/Data Buses AD15–AD0 16 ALE [PIO33] ARDY [PIO8] BHE [PIO34] {ADEN} BSIZE8 DEN [DS] [PIO30] DRQ1 DT/R [PIO29] HLDA {CLKSEL1} Bus Status and ...
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PIN CONNECTION DIAGRAM—160-PIN PQFP PACKAGE SDEN 3 SCLK 4 SDATA 5 PCS0 {USBSEL1} 6 PCS1 {USBSEL2} 7 PCS2 8 PCS3 9 PCS4 {CLKSEL2} 10 PCS5 11 PCS6 PCS7 14 ARDY 15 SRDY ...
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PIN AND SIGNAL TABLES Table 1 on page 10 and Table 2 on page 11 show the ...
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Table 1. PQFP Pin Assignments—Sorted by Pin Number Pin No. Name—Left Side Pin No. Name—Bottom Side Pin No SDEN 42 3 SCLK 43 4 SDATA 44 5 PCS0 {USBSEL1 PCS1 {USBSEL2 ...
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Table 1. PQFP Pin Assignments—Sorted by Pin Number Pin No. Name—Left Side Pin No. Name—Bottom Side Pin No. 38 AD2 78 39 AD10 Notes: 1. See Table 29, “PIOs Sorted by PIO Number,” on page ...
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Table 2. PQFP Pin Assignments—Sorted by Signal Name Signal Name Pin No. Signal Name AD11 47 INT4 AD12 52 INT5 AD13 67 INT6 AD14 87 INT7 AD15 93 INT8/PWD ALE 19 LCS/RAS0 ARDY 14 MCS0 {UCSX8} BHE {ADEN} 20 MCS1/CAS1 ...
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... An external or power-on reset is caused by asserting RES. An internal reset is initiated by the watchdog timer. A system reset is one that resets the Am186CC controller (the CPU plus the internal peripherals) as well as any external peripherals connected to RESOUT. An external reset always causes a system reset; an internal reset can optionally cause a system reset. ...
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... STI Asynchronous Ready is a true asynchronous ready that indicates to the Am186CC controller that the addressed memory space or I/O device will complete a data transfer. The ARDY pin is asynchronous to CLKOUT and is active High. To guarantee the number of wait states inserted, ARDY or SRDY must be synchronized to CLKOUT. If the falling edge of ARDY is not synchronized to CLKOUT as specified, an additional clock period can be added ...
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... DT/R is three-stated with a pullup during a bus-hold or reset condition. STI DMA Requests 1 and 0 indicate to the Am186CC controller that an external device is ready for a DMA channel to perform a transfer. DRQ1–[DRQ0] are STI level-triggered and internally synchronized. DRQ1–[DRQ0] are not latched and must remain active until serviced ...
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... Am186CC controller by deasserting HOLD. The controller responds by deasserting HLDA. If the Am186CC controller requires access to the bus (for example, for refresh), the controller deasserts HLDA before the external bus master deasserts HOLD. The external bus master must be able to deassert HOLD and allow the controller access to the bus ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) S2 — S1 — S0 {USBXCVR} WHB — WLB — WR [PIO15] CLOCKS/RESET/WATCHDOG TIMER CLKOUT — Am186™CC Communications Controller Data Sheet O Bus Cycle Status 2–0 indicate to the ...
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... Am186™CC Communications Controller Data Sheet Type Description STI Reset requires the Am186CC controller to perform a reset. When RES is asserted, the controller immediately terminates its present activity, clears its internal logic, and on the deassertion of RES, transfers CPU control to the reset address FFFF0h. ...
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... PIO4 Am186™CC Communications Controller Data Sheet STI Digital Power Supply pins supply power (+3.3 ± 0 the Am186CC controller logic. STI Analog Power Supply pin supplies power (+3.3 ± 0 the oscillators and PLLs. STI USB Power Supply pin supplies power (+3.3 ± 0 the USB block. ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Signal(s) [PCS7] PIO31 [PCS6] PIO32 [PCS5] PIO2 [PCS4] PIO3 {CLKSEL2} PCS3 — PCS2 — PCS1 [PIO14] {USBSEL2} PCS0 [PIO13] {USBSEL1} UCS {ONCE} DRAM [CAS1] MCS1 [CAS0] MCS2 [RAS1] [MCS3] PIO5 [RAS0] LCS ...
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... NMI pin must be asserted for at least one CLKOUT period. The board designer is responsible for properly terminating the NMI input. STI Maskable Interrupt Requests 8–0 indicate to the Am186CC controller that an external interrupt request has occurred. If the individual pin is not masked, the controller transfers program execution to the location specified by the associated STI interrupt vector in the controller’ ...
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... The additional internal interrupt used in PWD mode uses the same interrupt channel as [INT7]. If [INT7 used, it must be assigned to the shared interrupt channel. STI Timer Inputs 1–0 supply a clock or control signal to the internal Am186CC controller timers. After internally synchronizing a Low-to-High transition on STI [TMRIN1]–[TMRIN0], the microcontroller increments the timer. [TMRIN1]– ...
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... Serial Clock provides the clock for the synchronous serial interface to allow synchronous transfers between the Am186CC controller and a slave device. B Serial Data is used to transmit and receive data between the Am186CC controller and a slave device on the synchronous serial interface. O Serial Data Enable enables data transfers on the synchronous serial interface. ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Signal(s) DCE_TCLK_A [GCI_FSC_A] [PCM_FSC_A] [DCE_CTS_A] [PCM_TSC_A] PIO17 [DCE_RTR_A] PIO18 HDLC Channel B (DCE) [DCE_RXD_B] [PCM_RXD_B] PIO36 [DCE_TXD_B] [PCM_TXD_B] PIO37 [DCE_RCLK_B] [PCM_CLK_B] PIO40 [DCE_TCLK_B] [PCM_FSC_B] PIO41 [DCE_CTS_B] [PCM_TSC_B] PIO38 [DCE_RTR_B] PIO39 HDLC Channel ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Type Description Signal(s) [DCE_TXD_D] [TXD_U] (UART) [PCM_TXD_D] PIO20 DCE_RCLK_D [RTR_U] (UART) [PCM_CLK_D] PIO25 [DCE_TCLK_D] [CTS_U] (UART) [PCM_FSC_D] PIO24 [DCE_CTS_D] [CTS_HU] (High- Speed UART) [PCM_TSC_D] PIO46 [DCE_RTR_D] [RTR_HU] (High- Speed UART) PIO47 HDLC ...
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Table 4. Signal Descriptions (Continued) Multiplexed Signal Name Signal(s) [PCM_FSC_C] [DCE_TCLK_C] PIO23 [PCM_TSC_C] [DCE_CTS_C] PIO44 HDLC Channel D (PCM) [PCM_RXD_D] [RXD_U] (UART) DCE_RXD_D PIO26 [PCM_TXD_D] [TXD_U] (UART) [DCE_TXD_D] PIO20 [PCM_CLK_D] [RTR_U] (UART) DCE_RCLK_D PIO25 [PCM_FSC_D] [CTS_U] (UART) [DCE_TCLK_D] PIO24 [PCM_TSC_D] ...
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... USB External Transceiver Transmit Output Enable is an output that enables the external transceiver. UXVOE signals the external transceiver that USB data is being output by the Am186CC USB controller. When Low, this pin enables the transceiver output; when High, this pin enables the receiver. ...
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... PCM Highway, GCI, or raw DCE 28 Am186™CC Communications Controller Data Sheet microcontroller provides system cost and performance advantages for a wide range of communications applications. Figure block diagram of the Am186CC microcontroller, followed by sections providing an overview of the features of the Am186CC microcontroller. Serial Communications Peripherals Interrupt Controller Watchdog UART (17 Ext ...
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... Independent baud generator with clock input source programmable to use CPU or external clock input pin n General Circuit Interface (GCI) provides IOM-2 Terminal Mode connection – Glueless connection between the Am186CC microcontroller and GCI-based ISDN transceiver devices, such as the Am79C30/Am79C32 – Four-pin GCI connection – Terminal mode operation – ...
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... All string instruction references that use the DI register as an index USB peripheral functions in a device that also contains separate USB hub circuitry. In addition, the Am186CC USB controller supports the following unlimited number of device descriptors n A total of 6 endpoints: 1 control endpoint, 1 interrupt endpoint, and 4 data endpoints that can be configured as control, interrupt, bulk, or isochronous ...
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... Monitor and two Command/Indicate channels. Eight SmartDMA™ Channels The Am186CC microcontroller provides a total of 12 DMA channels. Eight of these channels are SmartDMA channels, which provide a method for transmission and reception of data across multiple memory buffers and a sophisticated buffer-chaining mechanism ...
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... SCLK and SDEN pins, as well as the shift order of bits on the SDATA pin (least- significant-bit first versus most-significant-bit first). The Am186CC SSI port also offers a programmable clock divisor (dividing the clock from 2 to 256 in power of 2 increments), a bidirectional transmit/receive shift register, and direct connection to AMD SLAC devices ...
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... Flash/EPROM memory systems. For systems where power consumption is a concern possible to disable the address from being driven on the AD bus on the Am186CC microcontroller during the normal address portion of the bus cycle for accesses to upper (UCS) and/or lower (LCS) address spaces. In this mode, the affected bus is placed in a high- impedance state during the address portion of the bus cycle ...
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... The Am186CC microcontroller provides the RD (Read) signal which acts as an output enable for memory or peripheral devices. The RD signal is Low when a word or byte is read by the Am186CC microcontroller. DRAM Support To support DRAM, the Am186CC microcontroller has a fully integrated DRAM controller that provides a glueless interface to 25– ...
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... AD15–AD0 (Write) LCS or UCS MCSx, PCSx Figure 3. Am186CC Controller Address Bus — Default Operation Am186™CC Communications Controller Data Sheet Clock Control The processor supports clock rates from MHz using an integrated cr ystal oscillator and PLL. Commercial and industrial temperature ratings are available ...
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... CLKOUT A19–A0 AD7–AD0 (Read) AD15–AD8 (Read) AD15–AD0 (Write) LCS or UCS Figure 4. Am186CC Controller—Address Bus Disable In Effect 36 Am186™CC Communications Controller Data Sheet Address Data Phase Phase Address Data Data Data t 4 ...
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... Am186CC microcontroller suitable for certain PC desktop applications such as a USB camera inter- face, ink-jet printers, and scanners. n General Communications Applications: The Am186CC microcontroller will also find a home in general embedded applications, because many de- vices will incorporate communications capability in the future. Many designs are adding HDLC capabil- ity as a robust means of inter- and intra-system communications ...
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I Figure 5. ISDN Terminal Adapter System Application Figure 6. ISDN to Ethernet Low-End Router System Application 38 Am186™CC Communications Controller Data Sheet ...
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Figure 7. 32-Channel Linecard System Application Am186™CC Communications Controller Data Sheet 39 ...
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... UART and High-Speed UART. The SSI and the timers (Timers 0, 1, and 2) derive their clocks from the system clock. Features The Am186CC controller clocks include the following features and characteristics: n Two independent crystal-controlled oscillators that use exter nal fundamental mode cr ystals or oscillators to generate the system input clock and the USB input clock ...
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... USB (USBX1). A 12-MHz source can be used with the system PLL in 2x mode and the USB PLL in 4x mode 24-MHz source can be used with the system in 1x mode and the USB in 2x mode. Am186CC Controller System Clock 1x 2x PLL ...
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System Operating Frequency 0 MHz 20 MHz 16 MHz 4x Mode 2x Mode 1x Mode PLL Bypass 0-MHz to 24-MHz Xtal or Clock Mode PLL Bypass Mode 1 The crystal oscillator is not guaranteed above 40 MHz. Figure 9. Suggested ...
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... Figure 11. External Interface to Support Clocks— External Clock Source Static Operation The Am186CC controller is a fully static design and can be placed in static mode by stopping the input clock. PLL bypass mode must be used with an external clock source. For PLL bypass mode, refer to the PLL Bypass Mode discussion below ...
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... Two basic strategies exist in designing systems containing the Am186CC controller. The first strategy is to design a homogenous system in which all logic components operate at 3.3 V. This provides the lowest overa ll power consumpti on. However tem designers may need to include devices for which 3 ...
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... USB system design. (At the time of this writing, the current USB specification and related information can be obtained on the Web at www.usb.org.) The Am186CC controller is guaranteed to meet all USB specifications. Required analog transceivers are integrated into the Am186CC controller. Am186™CC Communications Controller Data Sheet ...
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DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES Symbol Parameter V Output High voltage ( Output High voltage ( Output Low voltage ( 5-V tolerant Input High voltage IH5 V Input ...
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... Output capacitive load set bus set to data only n PIOs are disabled n Timer, serial port, refresh, and DMA are enabled Table 7 shows the values that are used to calculate the typical power consumption value for the Am186CC controller. Table 7. Typical Power Consumption Calculation MHz CC ...
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... THERMAL CHARACTERISTICS PQFP Package The Am186CC controller is specified for operation with case temperature ranges from 0•C to +100•C for 3.3 V ± 0.3 V (commercial). Case temperature is measured at the top center of the package as shown in Figure 14. The various temperatures and thermal resistances can be determined using the equations in Figure 15 with information given in Table 8 ...
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COMMERCIAL AND INDUSTRIAL SWITCHING CHARACTERISTICS AND WAVEFORMS In the switching waveforms that follow, several abbreviations are used to indicate the specific periods of a bus cycle. These periods are referred to as time states. A typical bus cycle is composed ...
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Table 9. Alphabetical Key to Switching Parameter Symbols Parameter No. Symbol t 49 ARYCH t 51 ARYCHL t 95 ARYHDSH t 89 ARYHDV t 52 ARYLCL t 96 ARYLDSH t 87 AVBL t 14 AVCH t 12 AVLL t 66 ...
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Table 9. Alphabetical Key to Switching Parameter Symbols (Continued) Parameter No. Description Symbol LCS active delay CLCSL t 16 MCS/PCS active delay CLCSV t 30 Data hold time CLDOX t 7 Data valid delay CLDV t 2 ...
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Table 9. Alphabetical Key to Switching Parameter Symbols (Continued) Parameter No. Symbol t 35 WHDEX t 34 WHDX t 33 WHLH t 32 WLWH USB Timing (Clocks UCHCK t 4 UCKHL t 1 UCKIN t 5 UCKLH t ...
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Table 9. Alphabetical Key to Switching Parameter Symbols (Continued) Parameter No. Description Symbol PCM (Master Delay time from CLK High to FSC High DCFH t 2 Delay time from CLK High to FSC Low DCFL GCI t 9 ...
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Table 10. Numerical Key to Switching Parameter Symbols Parameter No. Symbol 1 t DVCL 2 t CLDX 3 t CHSV 4 t CLSH 5 t CLAV 6 t CLAX 7 t CLDV 8 t CHDX 9 t CHLH 10 t ...
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Table 10. Numerical Key to Switching Parameter Symbols (Continued) Parameter No. Description Symbol 44 t CLKOUT High time CHCL 45 t CLKOUT rise time CH1CH2 46 t CLKOUT fall time CL2CL1 47 t SRDY transition setup time SRYCL 48 t ...
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Table 10. Numerical Key to Switching Parameter Symbols (Continued) Parameter No. Symbol DSHDIW 402 t COLV 403 t CHRAS 404 t CHCAS USB Timing (Clocks UCKIN 2 t UCLCK 3 t UCHCK 4 t UCKHL ...
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Table 10. Numerical Key to Switching Parameter Symbols (Continued) Parameter No. Description Symbol PCM (Master Delay time from CLK High to FSC High DCFH 2 t Delay time from CLK High to FSC Low DCFL GCI 1 t ...
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Switching Characteristics over Commercial and Industrial Operating Ranges In this section the following timings and timing waveforms are shown: n Read (page 58) n Write (page 61) n Software halt (page 64) n Peripheral (page 65) n Reset (page 66) ...
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Table 11. Read Cycle Timing Parameter No. Symbol Description 21 t DEN/DS inactive CEVDX 4 delay 22 t Control active CHCTV delay ALE High to LHAV address valid Read Cycle Timing Responses address float ...
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CLKOUT A19– AD15–AD0 ALE RD BHE LCS, UCS MCS3–MCS0, PCS7–PCS0 DEN, DS DT/R S2–S0 Notes not valid for the first fetch until the timing for parameter 3 (status active delay (t 60 Am186™CC Communications Controller ...
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Parameter No. Symbol Description General Timing Responses 3 t Status active delay CHSV 4 t Status and BHE CLSH inactive delay address and CLAV BHE valid delay 6 t Address hold CLAX 7 t Data valid delay ...
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Table 12. Write Cycle Timing Parameter No. Symbol Description Write Cycle Timing Responses 30 t Data hold time CLDOX 31 t Control inactive CVCTX 3,4 delay pulse width WLWH inactive to ALE WHLH 2 ...
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T4 CLKOUT A19– AD15—AD0 ALE WR WHB, WLB BHE LCS, UCS MCS3–MCS0, PCS7–PCS0 DEN DS DT/R S2–S0 Notes not valid for the first fetch until the timing for parameter 3 (status active delay (t Am186™CC ...
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Parameter No. Symbol Description 3 t Status active delay CHSV 4 t Status inactive CLSH delay address invalid CLAV delay 9 t ALE active delay CHLH 10 t ALE width LHLL 11 t ALE inactive delay CHLL ...
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Parameter No. Symbol Description 53 t Peripheral setup time INVCH 54 t Timer output delay CLTMV 55 t Queue status 0 output delay CHQ0SV 56 t Queue status 1 output delay CHQ1SV Notes: 1. All timing parameters are measured at ...
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Parameter No. Symbol Description 57 t RES setup time RESIN 61 t Reset delay CLRO Notes: 1. All timing parameters are measured at V are with the load values shown in Table 35, “Pin List Summary,” on page A-12. RES ...
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RES CLKOUT All Pinstrap 1, 2 Pins 1 AD15–AD0 All Other Outputs RESOUT Notes: 1. The pinstraps and AD bus are sampled during the assertion of RESOUT for system configuration purposes. 2. For a list of all the pinstraps, refer ...
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Parameter No. Symbol Description Ready Timing Requirements 47 t SRDY transition setup time SRYCL 48 t SRDY transition hold time CLSRY 49 t ARDY resolution transition setup time ARYCH 50 t ARDY active hold time CLARX 51 t ARDY inactive ...
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CLKOUT 1 ARDY (Normally Not-Ready System) 2 ARDY (Normally Ready System) Notes normally not ready system, wait states are added after T3 until normally ready system, a wait state is added if t ...
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CLKOUT HOLD HLDA AD15–AD0, DEN MCS3–MCS0, PCS7–PCS0 A19–A0, S6, RD, WR, BHE, DT/R, S2–S0, WHB, WLB, UCS, LCS, ALE Figure 26. Entering Bus Hold Waveforms Case 1 Case 2 CLKOUT HOLD HLDA AD15–AD0, DEN MCS3–MCS0), PCS7–PCS0) A19–A0, S6, RD, WR, ...
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Parameter No. Symbol Description CLKIN Requirements for 4x PLL Mode period CKIN Low time (1.5 V) CLCK High time (1.5 V) CHCK fall time CKHL (3.5 to ...
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CLKOUT Figure 28. System Clock Timing Waveforms—Active Mode (PLL 1x Mode) No. Symbol Description CLKIN Requirements for 4x PLL Mode 1 t USBX1 period UCKIN 2 t USBX1 Low time (1.5 V) UCLCK 3 t USBX1 High ...
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No. Symbol Description 1 t Pulse width High Pulse width Low Frame setup Frame hold/clock Frame delay/clock Frame width High WFH 7 t Data delay/clock ...
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Table 21. PCM Highway Timing (Timing Slave) No. Symbol Description 1 t PCM clock period CLKP 2 t PCM clock High PCM clock Low Hold time from CLK Low to FSC valid HCF 5 ...
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... PCM highway and (with proper configuration of the time slot assigners) could occupy different time slots. An external bus driver would need to be active for both Am186CC time slots. The open drain on the PCM_TSC_x pins permits them to be wired together to achieve this. ...
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Table 22. PCM Highway Timing (Timing Master) No. Symbol Description 1 t Delay time from CLK High to FSC High DCFH 2 t Delay time from CLK High to FSC Low DCFL Notes: 1. All timing parameters are measured at ...
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No. Symbol Description 1 t DCE clock period TCLKPER 2 t DCE clock High TCLKH 3 t DCE clock Low TCLKL 4 t DCE clock to output delay TCLKO 5 t DCE clock setup TCLKSU 6 t DCE clock hold ...
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Parameter No. Symbol Description 1 t Rise time ( pF Fall time ( pF Consecutive transition jitter (measured at crossover point) JR1 4 t Paired transition jitter (measured at crossover ...
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Parameter No. Symbol Description 1 t CLKOUT Low to SDEN valid CLEV 2 t CLKOUT Low to SCLK Low CLSL 3 t Data valid to SCLK High DVSH 4 t SCLK High to data invalid SHDX 5 t SCLK Low ...
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Parameter No. Symbol Description 1 t Data in setup DVCL 2 t Data in hold CLDX address valid delay CLAV 7 t Data valid delay CLDV address float delay CLAZ 20 t Control active ...
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CLKOUT AD15–AD0 A17, A15, A13, A11, A9, A7, A5, A3, A1 RAS0, RAS1 CAS0, RAS1 RD Figure 39. DRAM Read Cycle with Wait-States Waveform CLKOUT AD15–AD0 A17, A15, A13, A11, A9, A7, A5, A3, A1 RAS0, RAS1 CAS0, CAS1 WR ...
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CLKOUT AD15–AD0 A17, A15, A13, A11, A9, A7, A5, A3, A1 RAS0, RAS1 CAS0, CAS1 WR Figure 41. DRAM Write Cycle with Wait-States Waveform CLKOUT AD15–AD0 A17, A15, A13, A11, A9, A7, A5, A3, A1 RAS0, RAS1 CAS0, CAS1 RD ...
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... APPENDIX A—PIN TABLES This appendix contains pin tables for the Am186CC controller. Several different tables are included with the following characteristics: Power-on reset pin defaults including pin numbers and multiplexed functions—Table 27 on page A-2. Multiplexed signal trade-offs—Table 28 page A-5. ...
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Table 27. Power-On Reset (POR) Pin Defaults Pin Multiplexed POR Default Number Signal Bus Interface Unit A0 30 — — — — — — — — ...
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Table 27. Power-On Reset (POR) Pin Defaults (Continued) Pin Multiplexed POR Default Number Signal S6 54 — SRDY 15 — WHB 95 — WLB 96 — — Chip Selects LCS 131 RAS0 MCS1 127 CAS1 MCS2 128 CAS0 ...
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Table 27. Power-On Reset (POR) Pin Defaults (Continued) Pin Multiplexed POR Default Number Signal PIO5 129 MCS3 PIO6 147 INT8 PIO7 146 INT7 PIO9 124 DRQ0 PIO10 2 SDEN PIO11 3 SCLK PIO12 4 SDATA PIO16 25 RXD_HU PIO17 123 ...
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Table 28. Multiplexed Signal Trade-offs DESIRED FUNCTION LOST FUNCTION Interface Name Pin Interface Memory 131 SRAM LCS DRAM MCS1 127 MCS2 128 MCS3 129 CAS0 128 DRAM SRAM CAS1 127 RAS0 131 RAS1 129 Synchronous Communications Interfaces DCE_RXD_A DCE 118 ...
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Table 28. Multiplexed Signal Trade-offs (Continued) DESIRED FUNCTION LOST FUNCTION Interface Name Pin Interface PCM PCM_RXD_C 153 DCE Channel Channel PCM_TXD_C 154 C C PCM_CLK_C 150 PCM_FSC_C 149 PCM_TSC_C 152 PCM PCM_RXD_D 158 DCE Channel Channel PCM_TXD_D 159 D D ...
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Table 28. Multiplexed Signal Trade-offs (Continued) DESIRED FUNCTION LOST FUNCTION Interface Name Pin Interface PIO13 5 PIO14 6 PIO15 16 PIO16 25 PIO17 123 PIO18 122 PIO19 145 PIO20 159 PIO21 22 PIO22 150 PIO23 149 PIO24 157 PIO25 156 ...
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PIO No. Pin No. Multiplexed Signal PIO0 144 TMRIN1 PIO1 143 TMROUT1 PIO2 10 PCS5 PIO3 9 PCS4 PIO4 126 MCS0 PIO5 129 MCS3 PIO6 147 INT8 PIO7 146 INT7 PIO8 14 ARDY PIO9 124 DRQ0 PIO10 2 SDEN PIO11 ...
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Signal PIO No. Pin No. ALE PIO33 ARDY PIO8 BHE PIO34 CTS_HU PIO46 CTS_U PIO24 DCE_CTS_A PIO17 DCE_CTS_B PIO38 DCE_CTS_C PIO44 DCE_RCLK_B PIO40 DCE_RCLK_C PIO22 DCE_RTR_A PIO18 DCE_RTR_B PIO39 DCE_RTR_C PIO45 DCE_RXD_B PIO36 DCE_RXD_C PIO42 DCE_TCLK_B PIO41 DCE_TCLK_C PIO23 DCE_TXD_B ...
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... ONCE Mode Request asserted Low places the Am186CC microcontroller into ONCE mode. Otherwise, the controller operates normally. In ONCE mode, all pins are three- stated and remain in that state until a subsequent reset occurs. To guarantee that the controller does not inadvertently enter ONCE mode, {ONCE} has a weak internal pullup resistor that is active only during a reset ...
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... The signals must be held in the desired state for 4.5 system clock cycles after the deassertion of reset. Based on the pinstrap’s state at the time they are latched, certain features of the Am186CC controller are enabled or disabled. All external termination should be implemented with 10- kohm resistors on these signals “ Configuration Pins (Pinstraps),” ...
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Signal Name [Alternate Pin Function] No. {Pinstrap} Bus Interface Unit A10 50 A11 64 A12 65 A13 69 A14 70 ...
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Table 35. Pin List Summary (Continued) Signal Name [Alternate Pin Type Function] No. {Pinstrap} BHE [PIO34] 20 STI-PU [STI] [O] {ADEN} BSIZE8 94 DEN [DS] 18 [PIO30] STI-PU [STI] [O] [DRQ0] STI-PD 124 PIO9 STI-PD [STI] [O] DRQ1 105 STI-PD ...
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Table 35. Pin List Summary (Continued) Signal Name [Alternate Pin Function] No. {Pinstrap} PCS3 8 [PCS4] PIO3 9 STI-PU [STI] [O] {CLKSEL2} [PCS5] 10 PIO2 STI-PU [STI] [O] [PCS6] 11 PIO32 STI-PU [STI] [O] [PCS7] 13 PIO31 STI-PU [STI] [O] ...
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Table 35. Pin List Summary (Continued) Signal Name [Alternate Pin Type Function] No. {Pinstrap} [INT8] [PWD] 147 PIO6 STI-PU [STI] [O] NMI 115 Synchronous Communications Interfaces Channel A DCE_RXD_A [GCI_DD_A] 118 B-OD [PCM_RXD_A] DCE_TXD_A O-OD [GCI_DU_A] 119 B-OD [PCM_TXD_A] O-LS-OD ...
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Table 35. Pin List Summary (Continued) Signal Name [Alternate Pin Function] No. {Pinstrap} [DCE_RCLK_C] [PCM_CLK_C] 150 PIO22 STI-PD [STI] [O] [DCE_TCLK_C] [PCM_FSC_C] 149 PIO23 STI-PD [STI] [O] [DCE_CTS_C] [PCM_TSC_C] 152 PIO44 STI-PU [STI] [O] [DCE_RTR_C] 151 PIO45 STI-PU [STI] [O] ...
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Table 35. Pin List Summary (Continued) Signal Name [Alternate Pin Type Function] No. {Pinstrap} Synchronous Serial Interface [SCLK] 3 PIO11 STI-PU [STI] [O] [SDATA] 4 PIO12 STI-PU [STI] [O] [SDEN] 2 PIO10 STI-PD [STI] [O] Reserved Pins RSVD_104 104 [UXVRCV] ...
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Table 35. Pin List Summary (Continued) Signal Name [Alternate Pin Function] No. {Pinstrap} V 130 SS V 140 SS V 155 USB 82 SS A-18 Am186™CC Communications Controller Data Sheet Max POR ...
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APPENDIX B—PHYSICAL DIMENSIONS: PQR160, PLASTIC QUAD FLAT PACK (PQFP) Pin 160 25.35 REF Pin 1 I.D. Pin 40 3.20 3.60 0.25 Min Am186™CC Communications Controller Data Sheet 31.00 31.40 27.90 28.10 Pin 80 0.65 BASIC Pin 120 25.35 REF 27.90 ...
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B-2 Am186™CC Communications Controller Data Sheet ...
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... LV = low voltage Am186™CC Communications Controller Data Sheet AMD-K6™-2E Microprocessor AMD-K6™E Microprocessor Am5 86® ÉlanSC520 x Microcontroller ÉlanSC400 Microcontroller ÉlanSC410 Microcontroller Am186CC Communications Controller Am186ES and Am188ES Microcontrollers Am186ESLV & Am188ESLV Microcontrollers ™ Family Devices Am186ED Microcontroller Am186ER and Am188ER ...
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... The Am186CC/CH/CU customer development platform (CDP) is provided as a test and development platform for the Am186CC/CH/CU microcontrollers. The Am186CC/CH/CU CDP ships with the Am186CC microcontroller. Because this device suppor ts a superset of the features of the Am186CH HDLC and the Am186CU USB microcontrollers, the development platform can be used to evaluate the Am186CH and the Am186CU devices ...
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World Wide Web Home Page To access the AMD home page go to: www.amd.com. Then follow the Embedded Processors link for information about E86 and Comm86 products. Questions, requests, and input concerning AMD’ ...
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C-4 Am186™CC Communications Controller Data Sheet ...
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... AD15–AD0 signals, 14 address and data bus, 14, 17 address bus address bus disable in effect, 36 default operation, 35 description, 14, 17 ALE signal, 14 Am186CC controller architectural overview, 28 block diagram characteristics over commercial and industrial operating ranges, 46 detailed description, 28 distinctive characteristics, 1 general description, 1 ...
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... C-3 hotline and web, C-2 literature ordering, C-3 ordering the Am186CC controller, 2 third-party development support products, C-2 web home page, C characteristics over commercial and industrial operating ranges, 46 USB, 46 DCE (data communications equipment) ...
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N NMI signal operating ranges, 45 ordering information package PQFP physical dimensions, B-1 PCM (pulse-code modulation) highway signal descriptions, 25 timing (timing master), 76 timing (timing slave), 74 waveforms (timing master), 76 waveforms (timing slave), 75 ...
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A-5 pin and signal tables, 9 pin assignments sorted by signal name, 11 signal descriptions, 14 signals related to reset, 67 SmartDMA channels, 31 software halt cycle timing, 64 software halt cycle waveforms, 64 SRDY ...
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X X1 signal signal, 18 Am186™CC Communications Controller Data Sheet Index-5 ...
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Trademarks È 2000 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am5 86, Am386, and Am486 are registered trademarks, and AMD-K6, 3DNow!, Am186, Am188, CodeKit, Comm86, E86, ...