AM186CC-50KD\W C AMD (ADVANCED MICRO DEVICES), AM186CC-50KD\W C Datasheet - Page 44

• Manufacturer Part Number: AM186CC-50KD\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-50KD\W C

• Lead Free Status / Rohs Status: Compliant

POWER SUPPLY OPERATION
CMOS dynamic power consumption is proportional to
the square of the operating voltage multiplied by
capacitance and operating frequency. Static system
operation can reduce power consumption by enabling
the system designer to reduce operating frequency
when possible. However, operating voltage is always the
dominant factor in power consumption. By reducing the
operating voltage from 5 V to 3.3 V for any device, the
power consumed is reduced by 56%.
Reduction of system logic operating voltage dramatical-
ly reduces overall system power consumption. Addition-
al power savings can be realized as low-voltage mass
storage and peripheral devices become available.
Two basic strategies exist in designing systems
containing the Am186CC controller. The first strategy is
to design a homogenous system in which all logic
components operate at 3.3 V. This provides the lowest
overa ll power consumpti on. However, s ys tem
designers may need to include devices for which 3.3-V
versions are not available.
In the second strategy, the system designer must then
design a mixed 5-V/3.3-V system. This compromise
enables the system designer to minimize the system
logic power consumption while still including the
functionality of the 5-V features. The choice of a mixed
voltage system design also involves balancing design
complexity with the need for the additional features.
Power Supply Connections
Connect all V
supply and all ground pins to a common system
ground.
Input/Output Circuitry
To accommodate current 5-V systems, the Am186CC
controller has 5-V tolerant I/O drivers. The drivers
produce TTL-compatible drive output (minimum 2.4-V
logic High) and receive TTL and CMOS levels (up to
V
that should be considered with mixed 3.3-V/5-V
designs:
n During power-up, if the 3.3-V supply has a
44
CC
significant delay in achieving stable operation
relative to 5-V supply, then the 5-V circuitry in the
system may start driving the processor’s inputs
above the maximum levels (V
system design should ensure that the 5-V supply
does not exceed 2.6 V above the 3.3-V supply
during a power-on sequence.
+ 2.6 V). The following are some design issues
CC
pins together to the 3.3-V power
Am186™CC Communications Controller Data Sheet
CC
+ 2.6 V). The
n Preferably, all inputs are driven by sources that can
n Preferably, all pullup resistors are tied to the 3.3-V
PIO Supply Current Limit
Each programmable I/O output is able to sink or source
a sustained 16-mA drive current. However, only 40 mA
of sustained PIO current is allowed for each supply pin
(V
(V
To calculate the PIO current for each supply or ground
pin, sum the applicable current (source or sink) of all
PIO pins on either side of the pin (to the adjacent
corresponding pins), and divide the sum by two. The
resulting value should not exceed 40 mA for V
60 mA for V
Exclude the following pins from this calculation: 72
( V
(V
For example, to calculate the PIO current for pin 83
(V
pins between pin 71 (V
divide the sum by two.
CC
SS
CC
SS
S S
be three-stated during a system reset condition.
The system reset condition should persist until
stable V
ensure that the maximum input levels are not
exceeded during power-up conditions.
supply, which ensures that inputs requiring pullups
are not over stressed during power-up.
).
), and only 60 mA is allowed for each ground pin
_USB).
), total the sustained sinking current for all PIO
_ A) , 82 ( V
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SS
.
conditions are met. This should help
S S
_U SB ) , 77 ( V
SS
) and pin 100 (V
C C
_A ) , an d 7 9
SS
), and
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or