ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 145

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

Special Function IO
Register – SFIOR
2467S–AVR–07/09
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 60. Prescaler for Timer/Counter1, Timer/Counter2, and Timer/Counter3
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR0 and PSR321 bits is kept, hence keeping the corresponding
prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted
and can be configured to the same value without the risk of one of them advancing during con-
figuration. When the TSM bit is written to zero, the PSR0 and PSR321 bits are cleared by
hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1
When this bit is one, the Timer/Counter3, Timer/Counter1, and Timer/Counter2 prescaler will be
reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note
that Timer/Counter3, Timer/Counter1, and Timer/Counter2 share the same prescaler and a
reset of this prescaler will affect all three timers.
Bit
Read/Write
Initial Value
T3
CS30
CS32
CS31
The synchronization logic on the input pins (
TSM
R/W
7
0
TIMER/COUNTER3 CLOCK SOURCE
0
PSR321
CK
ExtClk
clk
R
6
–
0
T3
< f
clk_I/O
R
5
–
0
T2
/2) given a 50/50% duty cycle. Since the edge detector uses
CS20
CS22
CS21
R
4
–
0
Clear
TIMER/COUNTER2 CLOCK SOURCE
0
T3/T2/T1)
ACME
R/W
3
0
10-BIT T/C PRESCALER
clk
T2
PUD
R/W
is shown in
2
0
T1
CS10
CS12
CS11
PSR0
R/W
1
0
Figure
TIMER/COUNTER1 CLOCK SOURCE
PSR321
ATmega128
0
R/W
0
0
59.
clk
clk_I/O
T1
SFIOR
/2.5.
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