ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 172

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

172
ATmega128
Figure 79. USART Block Diagram
Note:
The dashed boxes in the block diagram separate the three main parts of the USART (listed from
the top): Clock Generator, Transmitter, and Receiver. Control registers are shared by all units.
The clock generation logic consists of synchronization logic for external clock input used by syn-
chronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only
used by Synchronous Transfer mode. The Transmitter consists of a single write buffer, a serial
Shift Register, parity generator and control logic for handling different serial frame formats. The
write buffer allows a continuous transfer of data without any delay between frames. The
Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the receiver includes a parity checker, control logic, a Shift Register and a two level
receive buffer (UDR). The receiver supports the same frame formats as the Transmitter, and can
detect frame error, data overrun and parity errors.
Refer to
placement.
Figure 1 on page
UCSRA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDR (Transmit)
2,
UDR (Receive)
UBRR[H:L]
Table 36 on page
UCSRB
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
78, and
CHECKER
PARITY
CLOCK
PARITY
OSC
DATA
Table 39 on page 81
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
TX
RX
Receiver
UCSRC
2467S–AVR–07/09
XCK
TxD
RxD
for USART pin