DS1267BE-010+ Maxim Integrated, DS1267BE-010+ Datasheet - Page 2

• Manufacturer Part Number: DS1267BE-010+
• Description: Digital Potentiometer ICs Digital Sextet Potentiometer
• Manufacturer: Maxim Integrated

Specifications of DS1267BE-010+

• Resistance: 10 kOhms
• Temperature Coefficient: 750 PPM / C
• Tolerance: 20 %
• Number Of Pots: Dual
• Taps Per Pot: 256
• Digital Interface: 3-Wire
• Description/function: Dual Digital Potentiometer Chip
• Operating Supply Voltage: 4.5 V to 5.5 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-20
• Minimum Operating Temperature: - 40 C
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 4.5 V

DS1267B
DESCRIPTION
The DS1267B Dual Digital Potentiometer Chip consists of two digitally controlled, solid-state
potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section
and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the
wiper on the resistive array is set by an 8-bit value that controls which tap point is connected to the wiper
output. Communication and control of the device are accomplished via a 3-wire serial port interface. This
interface allows the device wiper position to be read or written.
Both potentiometers can be connected in series (or stacked) for an increased total resistance with the
same resolution. For multiple-device, single-processor environments, the DS1267B can be cascaded or
daisy-chained. This feature provides for control of multiple devices over a single 3-wire bus.
The DS1267B is offered in three standard resistance values which include 10kΩ, 50kΩ, and 100kΩ
versions. Available packages for the device include a 16-pin SO and 20-pin TSSOP.
OPERATION
The DS1267B contains two 256-position potentiometers whose wiper positions are set by an 8-bit value.
These two 8-bit values are written to a 17-bit I/O shift register that is used to store the two wiper positions
and the stack select bit when the device is powered. A block diagram of the DS1267B is presented in
Figure 1.
Communication and control of the DS1267B are accomplished through a 3-wire serial port interface that
drives an internal control logic unit. The 3-wire serial interface consists of the three input signals:
,
RST
CLK, and DQ.
The
control signal is used to enable the 3-wire serial port operation of the device. The chip is
RST
selected when
is high;
must be high to begin any communication to the DS1267B. The CLK
RST
RST
signal input is used to provide timing synchronization for data input and output. The DQ signal line is
used to transmit potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shift
register of the DS1267B.
Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the
RST
signal input is low. Communication with the DS1267B requires the transition of the
input from a
RST
low state to a high state. Once the 3-wire port has been activated, data is entered into the part on the low
to high transition of the CLK signal inputs. Three-wire serial timing requirements are provided in the
timing diagrams of Figure 9(b)-(c).
Data written to the DS1267B over the 3-wire serial interface is stored in the 17-bit I/O shift register (see
Figure 2). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the
stack select bit. The composition of the I/O shift register is presented in Figure 2. Bit 0 of the I/O shift
register contains the stack select bit, which will be discussed in the section entitled Stacked
Configuration. Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value.
Bit 1 contains the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper setting.
Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position, with the
MSB for the wiper position occupying bit 9 and the LSB bit 16.
Maxim Integrated ............................................................................................................................................................................................. 2