MAX1068CCEG+ Maxim Integrated, MAX1068CCEG+ Datasheet - Page 12

• Manufacturer Part Number: MAX1068CCEG+
• Description: Analog to Digital Converters - ADC MultiCh 14-Bit 200ksps
• Manufacturer: Maxim Integrated

Specifications of MAX1068CCEG+

• Rohs: yes
• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 84 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
During the acquisition, the analog input (AIN_) charges
capacitor C
the T/H switches open. The retained charge on C
represents a sample of the input.
In hold mode, the capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to zero within the limits of 14-bit resolution. At the
end of the conversion, force CS high and then low to
reset the T/H switches back to track mode (AIN_),
where C
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
Figure 3. MAX1067 Functional Diagram
12
______________________________________________________________________________________
DAC
DAC
charges to the input signal again.
. At the end of the acquisition interval
AGND
SCLK
AIN0
AIN1
AIN2
AIN3
REF
DIN
CS
OSCILLATOR
ANALOG-INPUT
MULTIPLEXER
REFERENCE
AGND
BIAS
MULTIPLEXER
REFCAP
INPUT REGISTER
RAIL
AZ
CONTROL
BUFFER
DGND
DAC
SUCCESSIVE-APPROXIMATION
DAC
ANALOG-SWITCH FINE TIMING
AV
REGISTER
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(t
the signal. Use the following formula to calculate acqui-
sition time:
where R
impedance, R
than 729ns. A source impedance less than 200Ω does
not significantly affect the ADC’s performance. The
MAX1068 features a 16-bit-wide data-transfer mode
DD
ACQ
t
ACQ
) is the maximum time the device takes to acquire
COMPARATOR
MAX1067
IN
= 11(R
ACCUMULATOR
MEMORY
= 340Ω, R
DV
DD
DS(ON)
S
+ R
OUTPUT
IN
= 60Ω, and t
S
+ R
= the input signal’s source
DS(ON)
DOUT
EOC
)
✕
ACQ
45pF + 0.3µs
is never less