MAX1068CCEG+ Maxim Integrated, MAX1068CCEG+ Datasheet - Page 22

• Manufacturer Part Number: MAX1068CCEG+
• Description: Analog to Digital Converters - ADC MultiCh 14-Bit 200ksps
• Manufacturer: Maxim Integrated

Specifications of MAX1068CCEG+

• Rohs: yes
• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 84 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
4.8MHz (the maximum clock frequency). For lower
clock frequencies, ensure the minimum high and low
times are at least 93ns. External-clock-mode conver-
sions with SCLK rates less than 125kHz can reduce
accuracy due to leakage of the sampling capacitor.
The input data latches on the falling edge of SCLK. The
command/configuration/control register starts reading
data in on the falling edge of the first SCLK cycle imme-
diately following the falling edge of the frame sync
pulse and ends on the falling edge of the 16th SCLK
cycle. The MAX1068 selects the proper channel for
conversion on the falling edge of the 3rd clock cycle
and begins acquisition. Acquisition continues until the
rising edge of the 15th clock cycle. The MAX1068 sam-
ples the input on the rising edge of the 15th clock cycle.
On the rising edge of the 16th clock cycle, the MAX1068
outputs a frame sync pulse at DSPX. The frame sync
pulse alerts the DSP that the conversion results are
Figure 17. DSP External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing (MAX1068 Only)
Figure 18. DSP External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1068 Only)
22
STATE
DSPR
DOUT
DSPX
SCLK
STATE
ADC
DSPR
DOUT
DSPX
SCLK
DIN
CS
ADC
DIN
CS
______________________________________________________________________________________
X = DON
,
T CARE
MSB
1
1
MSB
t
ACQ
8
LSB
0
t
ACQ
X
X
8
LSB
0
X
MSB
X
X
X
X
16
X
about to be output at DOUT (MSB first) starting on the
rising edge of the 17th clock pulse. To read the entire
conversion result, 16 SCLK cycles are needed. Extra
clock pulses, occuring after the conversion result has
been clocked out and prior to the next rising edge of
DSPR, cause zeros to be clocked out of DOUT. The
MAX1068 external clock, DSP 16-bit-wide data-transfer
mode requires 32 clock cycles to complete.
Begin a new conversion by sending a new frame sync
pulse to DSPR followed by new configuration data.
Send the new DSPR pulse immediately after reading
the conversion result to realize maximum throughput.
Sending a new frame sync pulse in the middle of a con-
version immediately aborts the current conversion and
begins a new one. A rising edge on CS in the middle of
a conversion aborts the current conversion and places
the MAX1068 in shutdown.
MSB
t
CONV
16
t
CONV
24
LSB
S1
24
S0
LSB
IDLE
S1
32
S0
IDLE