IS43DR32800A-37CBL-TR ISSI, IS43DR32800A-37CBL-TR Datasheet - Page 18

• Manufacturer Part Number: IS43DR32800A-37CBL-TR
• Description: DRAM 256M (8Mx32) 266MHz Commercial Temp
• Manufacturer: ISSI

Specifications of IS43DR32800A-37CBL-TR

• Product Category: DRAM
• Rohs: yes
• Factory Pack Quantity: 1500

IS43DR32800A, IS43/46DR32801A
Guidelines for AC Parameters
1. DDR2 SDRAM AC Timing Reference Load
Figure "AC Timing Reference Load" represents the timing reference load used in defining the relevant timing
parameters of the part. It is not intended to be either a precise representation of the typical system environment or
a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation
tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test
conditions (generally a coaxial transmission line terminated at the tester electronics).
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing
reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS)
signal.
2. Slew Rate Measurement Levels
a) Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for single
ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = - 500 mV
and DQS - DQS = + 500 mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device.
b) Input slew rate for single ended signals is measured from Vref(dc) to VIH(ac),min for rising edges and from Vref(dc)
to VIL(ac),max for falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = - 250 mV to CK - CK = +
500 mV (+ 250 mV to - 500 mV for falling edges).
c) VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between
DQS and DQS for differential strobe.
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown in Figure "Slew Rate Test Load".
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of
the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method
by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships
are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode, these timing
relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing
methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via
the EMRS, the complementary pin, DQS, must be tied externally to VSS through a 20 Ω to 10 kΩ resistor to insure
proper operation.
18
VDDQ
VDDQ
DUT
DUT
DQS, DQS
DQS
DQS
DQ
DQ
Output
Figure - AC Timing Reference Load
Output
Test point
Timing
reference
point
Figure - Slew Rate Test Load
25Ω
25Ω
V
V
TT
TT
= V
= V
DDQ
DDQ
/2
/2
Integrated Silicon Solution, Inc. — www.issi.com
09/08/2010
Rev. 00E