IDT74SSTUBF32865ABK IDT, Integrated Device Technology Inc, IDT74SSTUBF32865ABK Datasheet

IDT74SSTUBF32865ABK

Manufacturer Part Number

IDT74SSTUBF32865ABK

Description

IC BUFFER 28BIT 1:2 REG 160-BGA

Manufacturer

IDT, Integrated Device Technology Inc

Datasheet

1.IDT74SSTUBF32865ABKG.pdf (16 pages)

Specifications of IDT74SSTUBF32865ABK

Number Of Bits

Logic Type

1:2 Registered Buffer with Parity

Supply Voltage

1.7 V ~ 1.9 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

160-BGA

Logic Family

SSTU

Logical Function

Reg Bfr W/ParityTst

Number Of Elements

Number Of Inputs

Number Of Outputs

High Level Output Current

-8mA

Low Level Output Current

8mA

Propagation Delay Time

3ns

Operating Supply Voltage (typ)

1.8V

Operating Supply Voltage (max)

1.9V

Operating Supply Voltage (min)

1.7V

Clock-edge Trigger Type

Posit/Negat-Edge

Polarity

Non-Inverting

Technology

CMOS

Frequency (max)

410(Min)MHz

Mounting

Surface Mount

Pin Count

160

Operating Temp Range

0C to 70C

Operating Temperature Classification

Commercial

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Other names

74SSTUBF32865ABK

Available stocks

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Company:

BOSTOCK HK LIMITED

Part Number:

IDT74SSTUBF32865ABK

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

IDT74SSTUBF32865ABK8

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IDT, Integrated Device Technology Inc

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10 000

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Bonase Electronics (HK) Co., Limited

Part Number:

IDT74SSTUBF32865ABKG

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PANASONIC

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Company:

BOSTOCK HK LIMITED

Part Number:

IDT74SSTUBF32865ABKG

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

IDT74SSTUBF32865ABKG8

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

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28-BIT 1:2 REGISTERED BUFFER WITH PARITY

Description

This 28-bit 1:2 registered buffer with parity is designed for

1.7V to 1.9V V

All clock and data inputs are compatible with the JEDEC

standard for SSTL_18. The control inputs are LVCMOS. All

outputs are 1.8 V CMOS drivers that have been optimized

to drive the DDR2 DIMM load. The IDT74SSTUBF32865A

operates from a differential clock (CLK and CLK). Data are

registered at the crossing of CLK going high, and CLK

going low.

The device supports low-power standby operation. When

the reset input (RESET) is low, the differential input

receivers are disabled, and undriven (floating) data, clock

and reference voltage (V

addition, when RESET is low all registers are reset, and all

outputs except PTYERR are forced low. The LVCMOS

RESET input must always be held at a valid logic high or

low level.

To ensure defined outputs from the register before a stable

clock has been supplied, RESET must be held in the low

state during power up.

In the DDR2 RDIMM application, RESET is specified to be

completely asynchronous with respect to CLK and CLK.

Therefore, no timing relationship can be guaranteed

between the two. When entering reset, the register will be

cleared and the outputs will be driven low quickly, relative to

the time to disable the differential input receivers. However,

when coming out of reset, the register will become active

quickly, relative to the time to enable the differential input

receivers. As long as the data inputs are low, and the clock

is stable during the time from the low-to-high transition of

RESET until the input receivers are fully enabled, the

design of the IDT74SSTUBF32865A must ensure that the

outputs will remain low, thus ensuring no glitches on the

output.

The device monitors both DCS0 and DCS1 inputs and will

gate the Qn outputs from changing states when both DCS0

and DCS1 are high. If either DCS0 and DCS1 input is low,

the Qn outputs will function normally. The RESET input has

priority over the DCS0 and DCS1 control and will force the

Qn outputs low and the PTYERR output high. If the

DCS-control functionality is not desired, then the

CSGateEnable input can be hardwired to ground, in which

case, the setup-time requirement for DCS would be the

same as for the other D data inputs.

28-BIT 1:2 REGISTERED BUFFER WITH PARITY

operation.

REF

) inputs are allowed. In

The IDT74SSTUBF32865A includes a parity checking

function. The IDT74SSTUBF32865A accepts a parity bit

from the memory controller at its input pin PARIN,

compares it with the data received on the D-inputs and

indicates whether a parity error has occurred on its

open-drain PTYERR pin (active LOW).

Features

•

Applications

•

28-bit 1:2 registered buffer with parity check functionality

Supports SSTL_18 JEDEC specification on data inputs

and outputs

Supports LVCMOS switching levels on CSGateEN and

RESET inputs

Low voltage operation: V

Available in 160-ball LFBGA package

DDR2 Memory Modules

Provides complete DDR DIMM solution with

ICS98ULPA877A or IDTCSPUA877A

Ideal for DDR2 400, 533, 667, and 800

IDT74SSTUBF32865A

= 1.7V to 1.9V

IDT74SSTUBF32865A

DATASHEET

7092/11

Related parts for IDT74SSTUBF32865ABK

IDT74SSTUBF32865ABK Summary of contents

Page 1

REGISTERED BUFFER WITH PARITY Description This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V V operation. DD All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are ...

Page 2

IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Block Diagram V REF PARIN D0 D21 DCS0 CSGateEN DCS1 DCKE0, DCKE1 DODT0, DODT1 RESET CLK CLK 28-BIT 1:2 REGISTERED BUFFER WITH PARITY (CS ACTIVE ...

Page 3

IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Pin Configuration 160-Ball BGA TOP VIEW 28-BIT 1:2 ...

Page 4

IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Ball Assignment Signal Group Signal Name DCKE0, DCKE1, Ungated Inputs DODT0, DODT1 Chip Select Gated Inputs Chip Select Inputs DCS0, DCS1 Re-Driven Parity Input Parity Error Program Inputs Clock Inputs Miscellaneous Inputs 28-BIT ...

Page 5

IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Function Table RESET DCS0 DCS1 ...

Page 6

IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Parity and Standby Function Table RESET DCS0 DCS1 ...

Page 7

IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these ...

Page 8

IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Operating Characteristics The RESET and CSGateEN inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is ...

Page 9

IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY DC Electrical Characteristics Over Operating Range Following Conditions Apply Unless Otherwise Specified: Operating Condition 0°C to +70° Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL ...

Page 10

IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Timing Requirements Over Recommended Operating Free-Air Temperature Range Symbol Parameter f Clock Frequency CLOCK t Pulse Duration; CLK, CLK HIGH or LOW W t Differential Inputs Active Time ACT t Differential Inputs Inactive ...

Page 11

IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range Parameter dV/dt_r dV/dt_f 1 dV/dt_∆ 1 Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 28-BIT 1:2 REGISTERED BUFFER ...

Page 12

IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Parity Logic Diagram PARIN CLOCK Register Timing CLK CLK PARIN PTYERR 28-BIT 1:2 REGISTERED BUFFER WITH ...

Page 13

IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Test Circuits and Waveforms (V DUT CLK Out CLK Inputs CLK Test Point R 100 L = Test Point Simulation Load Circuit LVCMOS RESET Input t ...

Page 14

IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Test Circuits and Waveforms (V DUT Out Load Circuit: High-to-Low Slew-Rate Adjustment Output 80% 20% dv_f dt_f Voltage Waveforms: High-to-Low Slew-Rate Adjustment DUT Out ...

Page 15

IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Ordering Information IDT XX SSTUBF XX Family Temp. Range 28-BIT 1:2 REGISTERED BUFFER WITH PARITY XXX XX X Device Type Package Shipping Carrier 8 BKG 865A COMMERCIAL TEMPERATURE GRADE Tape ...

Page 16

IDT74SSTUBF32865A 28-BIT 1:2 REGISTERED BUFFER WITH PARITY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States ...

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