MAX11048ECB+T Maxim Integrated, MAX11048ECB+T Datasheet - Page 17

• Manufacturer Part Number: MAX11048ECB+T
• Description: Analog to Digital Converters - ADC 16Bit 6Ch Simult Sampling
• Manufacturer: Maxim Integrated

Specifications of MAX11048ECB+T

• Rohs: yes
• Number Of Channels: 6
• Architecture: SAR
• Conversion Rate: 250 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 92.3 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 3478 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 6
• Voltage Reference: 4.096 V

In default mode (CR0 = 0), drive CONVST low to place
the devices into acquisition mode. All the input switch-
es are closed and the internal T/H circuits track the
respective input voltage. Keep the CONVST signal low
for at least 1µs (t
sampled voltages. On the rising edge of CONVST, the
switches are opened and the devices begin the conver-
sion on all the samples in parallel. EOC remains high
until the conversion is completed.
In the second mode (CR0 = 1), the devices enter acqui-
sition mode as soon as the previous conversion is com-
pleted. CONVST rising edge initiates the next sample
and conversion sequence. Drive CONVST low for at least
20ns to be valid.
Provide adequate time for acquisition and the requisite
quiet time in both modes to achieve accurate sampling
and maximum performance of the devices.
The CS and RD are active-low, digital inputs that control
the readout through the 16-/14-bit, parallel, 20MHz data
bus (D0–D15/13). After EOC transitions low, read the
conversion data by driving CS and RD low. Each low
period of RD presents the next channel’s result. When
CS or RD are high, the data bus is high impedance. CS
may be driven high between individual channel read-
outs or left low during the entire 8-channel readout.
The devices feature a precision, low-drift, internal
bandgap reference. Bypass REFIO with a 0.1µF capaci-
tor to AGND to reduce noise. The REFIO output voltage
may be used as a reference for other circuits. The output
impedance of REFIO is 10kΩ. Drive only high-impedance
circuits or buffer externally when using REFIO to drive
external circuitry.
Set the configuration register to disable the internal ref-
erence and drive REFIO with a high-quality external ref-
erence. To avoid signal degradation, ensure that the
integrated reference noise applied to REFIO is less
than 10µV in the bandwidth of up to 50kHz.
The devices have a built- in reference buffer to provide
a low-impedance reference source to the SAR convert-
ers. This buffer is used in both internal and external ref-
erence modes. The internal reference buffer output
feeds five RDC outputs. Connect all RDC outputs
ACQ
______________________________________________________________________________________
Reading Conversion Results
) to enable proper settling of the
External Reference
Internal Reference
Reference Buffer
Reference
Simultaneous-Sampling ADCs
4-/6-/8-Channel, 16-/14-Bit,
together. The reference buffer is externally compensat-
ed and requires at least 10µF on the RDC node for sta-
bility. For best performance, provide a total of at least
80µF on the RDC outputs.
Figures 8 and 9 show the transfer functions for all the
formats and devices. Code transitions occur halfway
between successive-integer LSB values.
For best performance, use PCBs with ground planes.
Ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines par-
allel to one another (especially clock lines), and avoid
running digital lines underneath the ADC package. A
single solid GND plane configuration with digital signals
routed from one direction and analog signals from the
other provides the best performance. Connect DGND,
AGND, and AGNDS pins on the devices to this ground
plane. Keep the ground return to the power supply for
this ground low impedance and as short as possible for
noise-free operation.
To achieve the highest performance, connect all the
RDC pins 22, 28, 35, 43, and 49 for the TQFN package
or pins 27, 33, 40, 48, and 54 for the TQFP package to
a local RDC plane on the PCB. In addition, on the TQFP
package, the RDC_SENSE pins 26 and 55 should be
directly connected to this RDC plane as well. Bypass
the RDC outputs with a total of at least 80µF of capaci-
tance. For example, if two capacitors are used, place
two 47µF, 10V X5R capacitors in 1210 case size as
close as possible to pins 22 and 49 (TQFN), or pins 27
and 54 (TQFP). Alternatively, if four capacitors are
used, place four 22µF, 10V X5R capacitors in 1210
case size as close as possible to pins 22, 28, 43, and
49 (TQFN), or pins 27, 33, 48, and 54 (TQFP). Ensure
that each capacitor is connected directly into the GND
plane with an independent via.
In cases where Y5U or Z5U ceramics are used, select
higher voltage rating capacitors to compensate for the
high-voltage coefficient of these ceramic capacitors,
thus ensuring that at least 80µF of capacitance is on
the RDC plane when the plane is driven to 4.096V by
the internal reference buffer. For example, at 4.096V, a
22µF X5R ceramic capacitor with a 10V rating diminish-
es to only 20µF, whereas the same capacitor in Y5U
ceramic at 4.096V decreases to about 13µF. However,
a 22µF Y5U ceramic capacitor with a 25V rating capac-
itor is approximately 20µF at 4.096V.
Layout, Grounding, and Bypassing
Transfer Functions
17