MAX11048ECB+T Maxim Integrated, MAX11048ECB+T Datasheet - Page 23

• Manufacturer Part Number: MAX11048ECB+T
• Description: Analog to Digital Converters - ADC 16Bit 6Ch Simult Sampling
• Manufacturer: Maxim Integrated

Specifications of MAX11048ECB+T

• Rohs: yes
• Number Of Channels: 6
• Architecture: SAR
• Conversion Rate: 250 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 92.3 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 3478 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 6
• Voltage Reference: 4.096 V

INL is the deviation of the values on an actual transfer
function from a straight line. For these devices, this
straight line is a line drawn between the end points of
the transfer function, once offset and gain errors have
been nullified.
DNL is the difference between an actual step width and
the ideal value of 1 LSB. For these devices, the DNL of
each digital output code is measured and the worst-case
value is reported in the Electrical Characteristics table. A
DNL error specification of greater than -1 LSB guaran-
tees no missing codes and a monotonic transfer function
for an SAR ADC. For example, -0.9 LSB guarantees no
missing code while -1.1 LSB results in missing code.
For the MAX11047/MAX11048/MAX11049, the offset
error is defined at code transition 0x0000 to 0x0001 in
offset binary encoding and 0x8000 to 0x8001 for two’s
complement encoding. For the MAX11057/MAX11058/
MAX11059, the offset error is defined at code transition
0x0000 to 0x0001 in offset binary encoding and 0x2000
to 0x2001 for two’s complement encoding. The offset
code transitions should occur with an analog input volt-
age of exactly 0.5 x (5/4.096) x V
GND for 16-bit devices or 0.5 x (5/4.096) x V
above GND for 14-bit devices. The offset error is
defined as the deviation between the actual analog
input voltage required to produce the offset code transi-
tion and the ideal analog input of 0.5 x (5/4.096) x
V
(5/4.096) x V
expressed in LSBs.
Gain error is defined as the difference between the
change in analog input voltage required to produce a
top code transition minus a bottom code transition,
subtracted from the ideal change in analog input volt-
age on (5/4.096) x V
(5/4.096) x V
For the devices, top code transition is 0x7FFE to
0x7FFF in two’s complement mode and 0xFFFE to
0xFFFF in offset binary mode. The bottom code transi-
tion is 0x8000 and 0x8001 in two’s complement mode
and 0x0000 and 0x0001 in offset binary mode. For the
MAX11057/MAX11058/MAX11059, top code transition
is 0x1FFE to 0x1FFF in two’s complement mode and
0x3FFE to 0x3FFF in offset binary mode. The bottom
code transition is 0x2000 and 0x2001 in two’s
REF
/65,536 above GND for 16-bit devices or 0.5 x
REF
REF
/16384 above GND for 14-bit devices,
______________________________________________________________________________________
x (16382/16384) for 14-bit devices.
REF
Differential Nonlinearity (DNL)
x (65,534/65,536) for 16-bit or
Integral Nonlinearity (INL)
REF
Definitions
/65,536 above
Offset Error
Gain Error
Simultaneous-Sampling ADCs
REF
/16384
4-/6-/8-Channel, 16-/14-Bit,
complement mode and 0x0000 to 0x0001 in offset
binary mode. For the devices, the analog input voltage
to produce these code transitions is measured and the
gain error is computed by subtracting (5/4.096) x V
x (65,534/65,536) or (5/4.096) x V
respectively, from this measurement.
For a waveform perfectly reconstructed from digital
samples, SNR is the ratio of the full-scale analog input
(RMS value) to the RMS quantization error (residual
error). The ideal, theoretical minimum analog-to-digital
noise is caused by quantization noise error only and
results directly from the ADC’s resolution (N bits):
where N = 16/14 bits. In reality, there are other noise
sources besides quantization noise: thermal noise, ref-
erence noise, clock jitter, etc. SNR is computed by tak-
ing the ratio of the RMS signal to the RMS noise, which
includes all spectral components not including the fun-
damental, the first five harmonics, and the DC offset.
SINAD is the ratio of the fundamental input frequency’s
RMS amplitude to the RMS equivalent of all the other
ADC output signals:
The ENOB indicates the global accuracy of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. With an
input range equal to the full-scale range of the ADC,
calculate the ENOB as follows:
THD is the ratio of the RMS of the first five harmonics of
the input signal to the fundamental itself. This is
expressed as:
where V
V
5
are the 2nd- through 5th-order harmonics.
SINAD dB
THD
1
is the fundamental amplitude and V
(
=
20
Signal-to-Noise Plus Distortion (SINAD)
)
SNR = (6.02 x N + 1.76)dB
=
×
ENOB
10
log
×
Effective Number of Bits (ENOB)
⎡
⎢
⎢
⎣
Total Harmonic Distortion (THD)
log
=
V
⎡
⎢
⎣
SINAD
2 2
Signal-to-Noise Ratio (SNR)
(
Noise Distortion
+
6 02
V
.
3 2
−
Signal
+
1 76
V
REF
+
.
1
V
4 2
x (16382/16384),
RMS
+
V
) )
5 2
RMS
2
through
⎤
⎥
⎥
⎦
⎤
⎥
⎦
REF
23