MAX1296BEEG Maxim Integrated, MAX1296BEEG Datasheet - Page 9

• Manufacturer Part Number: MAX1296BEEG
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1296BEEG

• Number Of Channels: 2/1
• Architecture: SAR
• Conversion Rate: 420 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Pseudo-Differential
• Snr: Yes
• Interface Type: Parallel
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QSOP-24
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: Internal 2.5 V or External

The sampling architecture of the ADCs’ analog com-
parator is illustrated in the equivalent input circuits of
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH5 for the MAX1294
(Figure 3a) and to CH0–CH1 for the MAX1296 (Figure
3b), while IN- is switched to COM (Table 2). In differen-
Figure 3a. MAX1294 Simplified Input Structure
Table 1. Control-Byte Functional Description
D2, D1, D0
D7, D6
BIT
D5
D4
D3
SINGLE-ENDED MODE: IN+ = CH0–CH5, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
COM
CH0
CH2
CH1
CH3
CH4
CH5
with +2.5V Reference and Parallel Interface
V
REF
ACQMOD
PD1, PD0
SGL/DIF
UNI/BIP
A2, A1, A0
INPUT
MUX
NAME
12-BIT CAPACITIVE DAC
Pseudo-Differential Operation
_______________________________________________________________________________________
C
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
CH0/CH1 AND CH2/CH3, AND CH4/CH5
SWITCH
–
12pF
C
HOLD
TRACK
SWITCH
+
PD1 and PD0 select the various clock and power-down modes.
T/H
ACQMOD = 0: Internal Acquisition Mode
ACQMOD = 1: External Acquisition Mode
SGL/DIF = 0: Pseudo-Differential Analog Input Mode
SGL/DIF = 1: Single-Ended Analog Input Mode
In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage
difference between two channels is measured (see Tables 2, 4).
UNI/BIP = 0: Bipolar Mode
UNI/BIP = 1: Unipolar Mode
In unipolar mode, an analog input signal from 0V to V
signal can range from -V
Address bits A2, A1, A0 select which of the 6/2 (MAX1294/MAX1296) channels is to be converted
(see Tables 2, 3).
0
0
1
1
R
800Ω
IN
HOLD
ZERO
Single-Ended and
0
1
0
1
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
COMPARATOR
Full Power-Down Mode. Clock mode is unaffected.
Standby Power-Down Mode. Clock mode is unaffected.
Normal Operation Mode. Internal clock mode selected.
Normal Operation Mode. External clock mode selected.
REF
/2 to +V
FUNCTIONAL DESCRIPTION
REF
tial mode, IN+ and IN- are selected from analog input
pairs (Table 3) and are internally switched to either of
the analog inputs. This configuration is pseudo-differen-
tial to the effect that only the signal at IN+ is sampled.
The return side (IN-) must remain stable within ±0.5
LSB (±0.1 LSB for best performance) with respect to
GND during a conversion. To accomplish this, connect
a 0.1µF capacitor from IN- (the selected input) to GND.
Figure 3b. MAX1296 Simplified Input Structure
/2.
SINGLE-ENDED MODE: IN+ = CH0–CH1, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR
COM
CH0
CH1
V
REF
REF
INPUT
MUX
can be converted; in bipolar mode, the
12-BIT CAPACITIVE DAC
C
CH0/CH1.
SWITCH
–
C
12pF
HOLD
TRACK
SWITCH
+
T/H
R
800Ω
IN
HOLD
ZERO
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
COMPARATOR
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