MAX1067BEEE Maxim Integrated, MAX1067BEEE Datasheet - Page 20

• Manufacturer Part Number: MAX1067BEEE
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1067BEEE

• Number Of Channels: 4
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 84 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QSOP-16
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Force DSPR high and DSEL low for the SPI/QSPI/
MICROWIRE-interface mode. The falling edge of CS
wakes the analog circuitry and allows SCLK to clock in
data (see Figure 13). DOUT changes from high-Z to logic
low after CS is brought low. Input data latches on the ris-
ing edge of SCLK. The command/configuration/control
register begins reading DIN on the first SCLK rising
edge and ends on the rising edge of the 8th SCLK
cycle. The MAX1068 selects the proper channel for
conversion on the rising edge of the 3rd SCLK cycle.
The internal oscillator activates 125ns after the rising
edge of the 16th SCLK cycle. Turn off the external
clock while the internal clock is on. Turning off SCLK
ensures lowest noise performance during acquisition.
Acquisition begins on the 2nd rising edge of the inter-
nal clock and ends on the falling edge of the 18th inter-
nal clock cycle. Each bit of the conversion result shifts
into memory as it becomes available. The conversion
result is available (MSB first) at DOUT on the falling
edge of EOC. The internal oscillator and analog circuit-
ry are shut down on the EOC high-to-low transition. Use
the EOC high-to-low transition as the signal to restart
the external clock (SCLK). To read the entire conver-
sion result, 16 SCLK cycles are needed. Extra clock
pulses, occurring after the conversion result has been
clocked out and prior to the rising edge of CS, cause
Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
Figure 15. SPI Internal Clock Mode, 16-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing (MAX1068 Only)
20
INTERNAL
STATE
DOUT
SCLK
______________________________________________________________________________________
ADC
EOC
CLK
DIN
CS
Internal Clock 16-Bit-Wide Data-Transfer and
1
X = DON
DATA
• • •
,
T CARE
8
9
X X X X X X X X
• • •
Scan Mode (MAX1068 Only)
16
2
t
ACQ
• • •
13
• • •
t
CONV
32
the conversion result to be shifted out again. The
MAX1068 internal-clock 16-bit-wide data-transfer mode
requires 32 external clock cycles and 32 internal clock
cycles for completion.
Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (t
conversion immediately aborts the conversion and
places the MAX1068 in shutdown.
Scan mode allows multiple channels to be scanned
consecutively or one channel to be scanned eight
times. Scan mode can only be enabled when using the
MAX1068 in internal clock mode. Enable scanning by
setting bits 4 and 3 in the command/configuration/con-
trol register (see Tables 3 and 4). In scan mode, conver-
sion results are stored in memory until the completion of
the last conversion in the sequence. Upon completion of
the last conversion in the sequence, EOC transitions
from high to low to indicate the end of the conversion
and shuts down the internal oscillator. Use the EOC
high-to-low transition as the signal to restart the external
clock (SCLK). DOUT provides the conversion results in
the same order as the channel conversion process. The
MSB of the first conversion is available at DOUT on the
falling edge of EOC. Figure 15 shows the timing dia-
gram for 16-bit-wide data transfer in scan mode.
34
• • •
t
ACQ
45
CSW
t
CONV
• • •
). Forcing CS high in the middle of a
64
MSB
17
POWER-DOWN
• • •
• • •
LSB
S1 S0
48
X