MAX1067BEEE Maxim Integrated, MAX1067BEEE Datasheet - Page 26

• Manufacturer Part Number: MAX1067BEEE
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1067BEEE

• Number Of Channels: 4
• Architecture: SAR
• Conversion Rate: 200 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 84 dB
• Interface Type: QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: QSOP-16
• Maximum Power Dissipation: 667 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

Multichannel, 14-Bit, 200ksps Analog-to-Digital
Converters
Table 8. Detailed SSPSTAT Register Contents
X = Don’t care.
Figure 22a. SPI Interface Connection for a PIC16/PIC17
Figure 22b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
26
DOUT*
SCLK
______________________________________________________________________________________
SMP
CKE
R/W
CS
D/A
UA
BF
P
S
*WHEN CS IS HIGH, DOUT = HIGH-Z
CONTROL BIT
MAX1067
MAX1068
V
DD
0
GND
DOUT
SCLK
1
CS
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
0
0
1ST BYTE READ
0
4
0
SETTINGS
SCK
SDI
I/O
D5
0
6
0
1
X
X
X
X
X
X
PIC16/17
V
DD
0
D4
0
D3
8
3RD BYTE READ
D2
SPI Data-Input Sample Phase. Input data is sampled at the middle of
the data output time.
SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the
serial clock.
Data Address Bit
Stop Bit
Start Bit
Read/Write Bit Information
Update Address
Buffer-Full Status Bit
20
SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
D1
The DSP mode of the MAX1068 only operates in exter-
nal clock mode. Figure 23 shows a typical DSP interface
connection to the MAX1068. Use the same oscillator as
the DSP to provide the clock signal for the MAX1068.
The DSP provides the falling edge at CS to wake the
MAX1068. The MAX1068 detects the state of DSPR on
the falling edge of CS (Figure 17). Logic low at DSPR
places the MAX1068 in DSP mode. After the MAX1068
enters DSP mode, CS can be left low. A frame sync
pulse from the DSP to DSPR initiates a conversion. The
MAX1068 sends a frame sync pulse from DSPX to the
DSP signaling that the MSB is available at DOUT. Send
another frame sync pulse from the DSP to DSPR to
begin the next conversion. The MAX1068 does not
operate in scan mode when using DSP mode.
LSB
D0
MSB
D13
S1
D12
S0
24
D11
HIGH-Z
D10
2ND BYTE READ
12
D9
D8
D7
DSP Interface
D6
16