MAX191BC/D Maxim Integrated, MAX191BC/D Datasheet - Page 20

• Manufacturer Part Number: MAX191BC/D
• Description: Analog to Digital Converters - ADC Low-Power 12-Bit Sampling ADC with Internal Reference and Power-Down
• Manufacturer: Maxim Integrated

Specifications of MAX191BC/D

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 100 KSPs
• Input Type: Differential
• Interface Type: Parallel, QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: +/- 5 V, + 5 V
• Maximum Power Dissipation: 1067 mW
• Number Of Converters: 1

between FFE (hex) and FFF (hex). Because interaction
occurs between adjustments, offset should be adjusted
before gain. For an input gain of two, remove R7 and R8.
The MAX191 accepts input voltages from AGND to V
while operating from a single supply, and V
when operating from dual supplies. Figure 22 shows
the bipolar input transfer function with AIN- connected
to midscale for single-supply operation and connected
to GND operating from dual supplies. When operating
from a single supply, the MAX191 can be configured
for bipolar operation on its pseudo-differential input.
Instead of using AIN- as an analog input return, AIN-
can be set to a different positive potential voltage
above ground (BIP pin is set high). The sampled ana-
log input (AIN+) can swing to any positive voltage
above and below AIN-, and the ADC performs bipolar
conversions with respect to AIN-. When operating from
dual supplies, the MAX191 full-scale range is from
-V
If the data bus connected to the ADC is active during a
conversion, crosstalk from the data pins to the ADC
comparator may generate errors. Slow-memory mode
avoids this problem by placing the µP in a wait state
during the conversion. In ROM mode, if the data bus is
active during the conversion, it should be isolated from
the ADC using three-state drivers.
The ADC generates considerable digital noise in ROM
mode when RD or CS go high and the output data dri-
vers are disabled after a conversion has started. This
noise can cause large errors if it occurs when the SAR
latches a comparator decision. To avoid this problem,
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
Figure 19b. Low Average-Power Mode Operation (External
Compensation)
20
REF
VREF
PD
______________________________________________________________________________________
RD
/2 to +V
0
OPEN CIRCUIT (FLOAT)
REF
2ms
/2.
12.5 s
200ms
Digital Bus Noise
SS
to V
DD
DD
RD and CS should be active for less than one clock
cycle. If this is not possible, RD or CS should go high at
the rising edge of CLK, since the comparator output is
always latched on falling edges of CLK.
Use printed circuit boards for best system performance.
Figure 20. Unipolar Transfer Function
Figure 21a. Trim Circuit for Gain (±0.5%)
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
V
IN
OUTPUT
CODE
0
AIN INPUT VOLTAGE (LSB)
1
MAX480
Layout, Grounding, Bypassing
2
3
10k
R3
R1
100
FULL-SCALE
TRANSITION
R4
10k
R2
49.9
1LSB =
FS–1LSB
FS = VREF
4096
FS
TO AIN+
FS