MAX191BC/D Maxim Integrated, MAX191BC/D Datasheet - Page 8

• Manufacturer Part Number: MAX191BC/D
• Description: Analog to Digital Converters - ADC Low-Power 12-Bit Sampling ADC with Internal Reference and Power-Down
• Manufacturer: Maxim Integrated

Specifications of MAX191BC/D

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 100 KSPs
• Input Type: Differential
• Interface Type: Parallel, QSPI, Serial (SPI, Microwire)
• Operating Supply Voltage: +/- 5 V, + 5 V
• Maximum Power Dissipation: 1067 mW
• Number Of Converters: 1

Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
Figure 1. Load Circuits for Access Time
Figure 2. Load Circuits for Bus-Relinquish Time
The MAX191 uses successive approximation and input
track/hold (T/H) circuitry to convert an analog input sig-
nal to a 12-bit digital output. Flexible control logic pro-
vides easy interface to microprocessors (µPs), so most
applications require only the addition of passive com-
ponents. No external hold capacitor is required for the
T/H. Figure 3 shows the MAX191 in its simplest opera-
tional configuration.
The sampling architecture of the ADC’s analog com-
parator is illustrated in the Equivalent Input Circuit
(Figure 4). A capacitor switching between the AIN+
and AIN- inputs acquires the signal at the ADC’s ana-
log input. At the end of the conversion, the capacitor
reconnects to AIN+ and charges to the input signal.
An external input buffer is usually not needed for low-
bandwidth input signals (<100Hz) because the ADC
8
_______________Detailed Description
DN
DN
_______________________________________________________________________________________
a. High-Z to V
3k
3k
a. V
DGND
OH
DGND
OH
to High-Z
and V
OL
C
to V
L
10pF
OH
Pseudo-Differential Input
b. High-Z to V
DN
DN
b. V
+5V
OL
+5V
OL
to High-Z
3k
C
and V
DGND
L
3k
10pF
DGND
OH
to V
OL
disconnects from the input during the conversion. In
unbuffered applications, an input filter capacitor
reduces conversion noise, but also may limit input
bandwidth.
When converting a single-ended input signal, AIN-
should be connected to AGND. If a differential signal is
connected, consider that the configuration is pseudo
differential—only the signal side to the input channel is
held by the T/H. The return side (AIN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. Accomplish this
by connecting a 0.1µF capacitor from AIN- to AGND.
The T/H enters its tracking mode when the ADC is des-
elected (CS pin is held high and BUSY pin is high).
Hold mode starts approximately 25ns after a conver-
sion is initiated. The variation in this delay from one
conversion to the next (aperture jitter) is about 50ps.
Figures 6–10 detail the T/H and interface timing for the
Figure 3. Operational Diagram
4.7 F
NOTE: C1 120pF GENERATES 1MHz NOMINAL CLOCK.
0.1 F
OUTPUT
STATUS
0.1 F
OPEN
10
11
12
1
3
4
5
6
7
8
9
AIN+
AIN-
VREF
REFADJ
BUSY
PD
AGND
BIP
DO/DB
D1/D9
DGND
Analog Input—Track/Hold
0V TO -5V
2
V
P DATA BUS
SS
MAX191
D6/SCLK
CLK/SCLK
D5/SSTRB
D7/DOUT
D3/D11
D2/D10
HBEN
PAR
V
OUT
D4
CS
RD
DD
23
18
17
16
15
14
13
24
22
21
20
19
+5V
C1
SERIAL/PARALLEL
INTERFACE MODE
INPUTS
P CONTROL