MAX1169BEUD Maxim Integrated, MAX1169BEUD Datasheet - Page 11

• Manufacturer Part Number: MAX1169BEUD
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1169BEUD

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 58 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 90 dB
• Interface Type: I2C, Serial
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TSSOP-14
• Maximum Power Dissipation: 864 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

The MAX1169 ADC uses successive-approximation
conversion (SAR) techniques and on-chip track-and-
hold (T/H) circuitry to capture and convert an analog
signal to a serial 16-bit digital output.
The MAX1169 performs a unipolar conversion on its
single analog input using its internal 4MHz clock. The
full-scale analog input range is determined by the inter-
nal reference or by an externally applied reference volt-
age ranging from 1V to V
The flexible 2-wire serial interface provides easy con-
nection to microcontrollers (μCs) and supports data
rates up to 1.7MHz. Figure 3 shows the simplified func-
tional diagram for the MAX1169 and Figure 4 shows the
typical application circuit.
To maintain a low-noise environment, the MAX1169
provides separate analog and digital power-supply
inputs. The analog circuitry requires a +5V supply and
consumes only 900μA at sampling rates up to
58.6ksps. The digital supply voltage accepts voltages
from +2.7V to +5.5V to ensure compatibility with low-
PIN
10
11
12
13
14
1
2
3
4
5
6
7
8
9
REFADJ
AGNDS
NAME
DGND
AGND
DVDD
ADD2
ADD1
ADD0
AVDD
ADD3
SDA
SCL
REF
AIN
______________________________________________________________________________________
Detailed Description
AVDD
Digital Ground
Clock Input
Data Input/Output
Address Select Input 2
Address Select Input 1
Address Select Input 0
Digital Power Input. Bypass to DGND with a 0.1μF capacitor.
Analog Power Input. Bypass to AGND with a 0.1μF capacitor.
Analog Ground
Analog Input
Analog Signal Ground. Negative reference for analog input. Connect to AGND.
Internal Reference Output and Reference Buffer Input. Bypass to AGND with a 0.1μF capacitor.
Connect REFADJ to AVDD to disable the internal bandgap reference and reference-buffer amplifier.
Reference Buffer Output and External Reference Input. Bypass to AGND with a 10μF capacitor
when using the internal reference.
Address Select Input 3
.
58.6ksps, 16-Bit, 2-Wire Serial ADC
Power Supply
voltage ASICs. The MAX1169 wakes up in shutdown
mode when power is applied irrespective of the AVDD
and DVDD sequence.
The MAX1169 analog input contains a T/H capacitor,
T/H switches, comparator, and a switched capacitor
digital-to-analog converter (DAC) (Figure 5).
As shown in Figure 11c, the MAX1169 acquisition peri-
od is the two clock cycles prior to the conversion peri-
od. The T/H switches are normally in the hold position.
During the acquisition period, the T/H switches are in
the track position and C
signal. Before a conversion begins, the T/H switches
move to the hold position retaining the charge on C
as a sample of the analog input signal.
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
zero within the limits of 16-bit resolution. This is equiva-
lent to transferring a charge of 35pF × (V
from C
forming a digital representation of the analog input sig-
nal. During the conversion period, the MAX1169 holds
SCL low (clock stretching).
FUNCTION
T/H
to the binary weighted capacitive DAC,
in a 14-Pin TSSOP
Analog Input and Track/Hold
T/H
charges to the analog input
Pin Description
AIN
- V
AGNDS
T/H
11
)