MAX1169BEUD Maxim Integrated, MAX1169BEUD Datasheet - Page 13

• Manufacturer Part Number: MAX1169BEUD
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1169BEUD

• Number Of Channels: 1
• Architecture: SAR
• Conversion Rate: 58 KSPs
• Resolution: 16 bit
• Input Type: Single-Ended
• Snr: 90 dB
• Interface Type: I2C, Serial
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TSSOP-14
• Maximum Power Dissipation: 864 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

where R
f
(the number of bits of resolution), C
of C
(the T/H switch resistances).
To improve the input-signal bandwidth under AC
conditions, drive AIN with a wideband buffer
(>4MHz) that can drive the ADC’s input capacitance
and settle quickly (see the Input Buffer section).
An RC filter at AIN reduces the input track-and-hold
switching transient by providing charge for C
The MAX1169 features input-tracking circuitry with a
4MHz small-signal bandwidth. The 4MHz input band-
width makes it possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under-
sampling techniques. Use anti-alias filtering to avoid
high-frequency signals being aliased into the frequency
band of interest.
Internal electrostatic discharge (ESD) protection diodes
clamp AIN, REF, and REFADJ to AVDD and AGNDS/
AGND (Figure 6). These diodes allow the analog inputs
to swing from (V
causing damage to the device. For accurate conver-
sions, the inputs must not go more than 50mV beyond
their rails.
If the analog inputs exceed 300mV beyond their
rails, limit the current to 2mA.
The MAX1169 contains an internal 4MHz oscillator that
drives the SAR conversion clock. During conversion, SCL
is held low (clock stretching). An internal register stores
Figure 5. Equivalent Input Circuit
SCL
*MINIMIZE R
CHARGE TO THE ANALOG SIGNAL SOURCE VOLTAGE WITHIN THE ALLOTTED TIME (t
T/H
is the maximum system SCL frequency, N is 16
*R
SOURCE
ANALOG
SIGNAL
SOURCE
SOURCE
and input stray capacitance), and R
SOURCE
Analog Input Range and Protection
TO ALLOW THE TRACK-AND-HOLD CAPACITANCE (C
AIN
AGNDS
AGND
is the analog input source impedance,
TRACK
HOLD
______________________________________________________________________________________
- 0.3V) to (V
C
T/H
Analog Input Bandwidth
58.6ksps, 16-Bit, 2-Wire Serial ADC
AVDD
REF
IN
Internal Clock
is 35pF (the sum
CAPACITIVE
DAC
+ 0.3V) without
MAX1169
T/H
) TO
T/H
IN
is 800Ω
.
ACQ
).
data when the conversion is in progress. When the
MAX1169 releases SCL, the master reads the conversion
results at any clock rate up to 1.7MHz (Figure 11).
The MAX1169 features an I
interface consisting of a bidirectional serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facili-
tate bidirectional communication between the
MAX1169 and the master at rates up to 1.7MHz. The
master (typically a microcontroller) initiates data trans-
fer on the bus and generates SCL.
SDA and SCL require pullup resistors (500Ω or greater,
Figure 4). Optional resistors (24Ω) in series with SDA
and SCL protect the device inputs from high-voltage
spikes on the bus lines. Series resistors also minimize
crosstalk and undershoot of the bus signals.
One data bit is transferred during each SCL clock
cycle. Nine clock cycles are required to transfer the
data into or out of the MAX1169. The data on SDA must
remain stable during the high period of the SCL clock
pulse as changes in SDA while SCL is high are control
signals (see the START and STOP Conditions section).
Both SDA and SCL idle high.
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP con-
dition (P), a low-to-high transition on SDA while SCL is
high (Figure 7). The STOP condition frees the bus and
places all devices in F/S mode (see the Bus Timing
section). Use a repeated START condition (Sr) in place
of a STOP condition to leave the bus active and in its
current timing mode (see the HS Mode section).
Figure 6. Internal Protection Diodes
REFADJ
AGNDS
AGND
AVDD
in a 14-Pin TSSOP
REF
AIN
START and STOP Conditions
2
C-compatible, 2-wire serial
Digital Interface
MAX1169
Bit Transfer
13