MAX128AEAI Maxim Integrated, MAX128AEAI Datasheet - Page 11

• Manufacturer Part Number: MAX128AEAI
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX128AEAI

• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 8 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended
• Snr: Yes
• Interface Type: I2C, Serial
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: SSOP-28
• Maximum Power Dissipation: 762 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

The MAX127/MAX128 have a 7-bit-long slave address.
The first four bits (MSBs) of the slave address have
been factory programmed and are always 0101. The
logic state of the address input pins (A2–A0) determine
the three LSBs of the device address (Figure 3). A max-
imum of eight MAX127/MAX128 devices can therefore
be connected on the same bus at one time.
A2–A0 may be connected to V
may be actively driven by TTL or CMOS logic levels.
The eighth bit of the address byte determines whether
the master is writing to or reading from the MAX127/
MAX128 (R/W = 0 selects a write condition. R/W = 1
selects a read condition).
Figure 3. Address Byte
Figure 5. 2-Wire Serial-Interface Timing Diagram
SCL
SDA
SDA
SLAVE ADDRESS BITS A2, A1, AND A0 CORRESPOND TO THE LOGIC STATE
OF THE ADDRESS INPUT PINS A2, A1, AND A0.
SCL
t
HD
0
START CONDITION
,
STA
1
0
______________________________________________________________________________________
SLAVE ADDRESS
t
LOW
1
t
R
t
A2
SU
t
HIGH
,
DAT
A1
t
DD
F
or DGND, or they
Slave Address
Multirange, +5V, 12-Bit DAS with
A0
t
HD
,
DAT
LSB
R/W
ACK
t
SU
REPEATED START CONDITION
,
STA
The master signals the beginning of a transmission with
a START condition (S), which is a high-to-low transition
on SDA while SCL is high. When the master has fin-
ished communicating with the slave, the master issues
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high (Figure 4). The bus is then
free for another transmission. Figure 5 shows the timing
diagram for signals on the 2-wire interface. The
address-byte, control-byte, and data-byte are transmit-
ted between the START and STOP conditions. The SDA
state is allowed to change only while SCL is low, except
for the START and STOP conditions. Data is transmitted
in 8-bit words. Nine clock cycles are required to trans-
fer the data in or out of the MAX127/MAX128. (Figures
9 and 10).
Figure 4. START and STOP Conditions
2-Wire Serial Interface
SDA
SCL
START CONDITION
t
HD
,
STA
t
SU
,
STO
STOP CONDITION
Conversion Control
t
BUF
STOP CONDITION
START CONDITION
11