MAX1203BCAP-T Maxim Integrated, MAX1203BCAP-T Datasheet - Page 20

• Manufacturer Part Number: MAX1203BCAP-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1203BCAP-T

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: 71 dB
• Interface Type: 4-Wire (SPI, Microwire, TMS320)
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-20
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

5V, 8-Channel, Serial, 12-Bit ADCs
with 3V Digital Interface
Figure 14a. MAX1202 Supply Current vs. Sample Rate/Second,
FULLPD, 400kHz Clock
With both the MAX1202 and MAX1203, an external refer-
ence can be placed at either the input (REFADJ) or the
output (REF) of the internal reference-buffer amplifier. The
REFADJ input impedance is typically 20kΩ for the
MAX1202, and higher than 100kΩ for the MAX1203,
where the internal reference is omitted. At REF, the DC
input resistance is a minimum of 12kΩ. During conversion,
an external reference at REF must deliver up to 350µA DC
load current and have an output impedance of 10Ω or
less. If the reference has higher output impedance or is
noisy, bypass it close to the REF pin with a 4.7µF capacitor.
Using the buffered REFADJ input makes buffering of the
external reference unnecessary. When connecting an
external reference directly at REF, disable the internal
buffer by tying REFADJ to V
bias current to REFADJ can be as much as 25µA with
REFADJ tied to V
GND to minimize the input bias current in power-down.
Figure 15 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 16 shows the bipolar
I/O transfer function. Code transitions occur halfway
between successive-integer LSB values. Output coding
is binary with 1LSB = 1.00mV (4.096V/4096) for unipo-
lar operation, and 1LSB = 1.00mV [(4.096V/2 - -4.096V/
2)/4096] for bipolar operation.
Figure 17 shows how to adjust the ADC gain in applica-
tions that use the internal reference. The circuit provides
±1.5% (±65LSBs) of gain adjustment range.
20
______________________________________________________________________________________
1000
100
10
1
Transfer Function and Gain Adjust
0
2ms FASTPD WAIT
400kHz EXTERNAL CLOCK
INTERNAL COMPENSATION
50
CONVERSIONS PER CHANNEL PER SECOND
DD
100
(MAX1202 only). Pull REFADJ to
150
FULL POWER-DOWN
200
DD
250
. In power-down, the input
300
External Reference
350
8 CHANNELS
1 CHANNEL
400
450
500
For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 18 shows the recommended system ground
connections. Establish a single-point analog ground
Figure 14b. MAX1202/MAX1203 Supply Current vs. Sample
Rate/Second, FASTPD, 2MHz Clock
Figure 14c. Typical Power-Up Delay vs. Time in Shutdown
10,000
1000
100
10
3.0
2.5
2.0
1.5
1.0
0.5
Layout, Grounding, and Bypassing
0
0
0.0001
2k
CONVERSIONS PER CHANNEL PER SECOND
8 CHANNELS
0.001
4k
TIME IN SHUTDOWN (sec)
MAX1202/MAX1203
FAST POWER-DOWN
6k
2MHz EXTERNAL CLOCK
EXTERNAL COMPENSATION
50µs WAIT
0.01
8k
10k
0.1
12k
1
14k
1 CHANNEL
16k
10
18k