ispLSI 3160-125LB272 Lattice, ispLSI 3160-125LB272 Datasheet

ispLSI 3160-125LB272

Manufacturer Part Number

ispLSI 3160-125LB272

Description

CPLD - Complex Programmable Logic Devices USE ispMACH 4000V

Manufacturer

Lattice

Datasheet

1.ISPLSI_3160-70LB272.pdf (15 pages)

Specifications of ispLSI 3160-125LB272

Product Category

CPLD - Complex Programmable Logic Devices

Memory Type

EEPROM

Number Of Macrocells

160

Maximum Operating Frequency

125 MHz

Delay Time

10 ns

Number Of Programmable I/os

160

Operating Supply Voltage

5 V

Maximum Operating Temperature

+ 70 C

Minimum Operating Temperature

0 C

Package / Case

BGA

Mounting Style

SMD/SMT

Factory Pack Quantity

Supply Current

275 mA

Supply Voltage - Max

5.25 V

Supply Voltage - Min

4.75 V

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• HIGH-DENSITY PROGRAMMABLE LOGIC

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

• ispDesignEXPERT™ – LOGIC COMPILER AND COM-

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

3160_09

Features

— 160 I/O Pins

— 7000 PLD Gates

— 320 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

—

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

— 5V In-System Programmability (ISP™) Using

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Debugging

— Complete Programmable Device Can Combine Glue

— Five Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Mini-

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

— PC and UNIX Platforms

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

Market, and Improved Product Quality

Lattice ISP or Boundary Scan Test (IEEE 1149.1)

Protocol

Machines, Address Decoders, etc.

Logic and Structured Designs

mize Switching Noise

Interconnectivity

Tools, Timing Simulator and ispANALYZER™

max = 125 MHz Maximum Operating Frequency

pd = 7.5 ns Propagation Delay

CMOS

TECHNOLOGY

In-System Programmable High Density PLD

The ispLSI 3160 is a High-Density Programmable Logic

Devices containing 320 Registers, 160 Universal I/O

pins, five Dedicated Clock Input Pins, five Output Routing

Pools (ORP) and a Global Routing Pool (GRP) which

allows complete inter-connectivity between all of these

elements. The ispLSI 3160 features 5V in-system pro-

grammability and in-system diagnostic capabilities. The

ispLSI 3160 offers non-volatile reprogrammability of the

logic, as well as the interconnect to provide truly

reconfigurable systems.

The basic unit of logic on the ispLSI 3160 device is the

Twin Generic Logic Block (Twin GLB) labelled A0, A1...E3.

There are a total of 20 of these Twin GLBs in the ispLSI

3160 device. Each Twin GLB has 24 inputs, a program-

mable AND array and two OR/Exclusive-OR Arrays, and

eight outputs which can be configured to be either com-

binatorial or registered. All Twin GLB inputs come from

the GRP.

Functional Block Diagram

Description

Global Routing Pool

ORP

ispLSI

(GRP)

Array

ORP

D Q

December 2003

Twin

GLB

3160

Scan TAP

Boundary

ISP and

Related parts for ispLSI 3160-125LB272

ispLSI 3160-125LB272 Summary of contents

Page 1

... The basic unit of logic on the ispLSI 3160 device is the Twin Generic Logic Block (Twin GLB) labelled A0, A1...E3. There are a total these Twin GLBs in the ispLSI 3160 device. Each Twin GLB has 24 inputs, a program- ...

Page 2

... Functional Block Diagram Figure 1. ispLSI 3160 Functional Block Diagram Generic TOE Logic Blocks I/O 1 I/O 0 I I/O 5 I/O 4 I/O 7 I/O 6 I/O 8 I/O 9 I I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I I/O 20 I/O 21 I/O 22 I/O 23 I/O 25 I/O 24 I I/O 29 I/O 28 I/O 31 I/O 30 I/O 32 I/O 33 I I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 ...

Page 3

... Megablock. The Megablock is defined by the resources that it shares. The outputs of one pair of Twin GLBs are connected to a set of 16 I/O cells by the ORP. The ispLSI 3160 device contains five of these Megablocks. The GRP has as its inputs the outputs from all of the Twin GLBs and all of the inputs from the bidirectional I/O cells ...

Page 4

... CC V Input Low Voltage IL V Input High Voltage IH Capacitance (T =25°C,f=1.0 MHz) A SYMBOL PARAMETER C I/O Capacitance 1 C Clock Capacitance 2 Data Retention Specifications PARAMETER Data Retention ispLSI Erase/Reprogram Cycles Specifications ispLSI 3160 1 +1.0V CC +1.0V CC PARAMETER TYPICAL 10 15 MINIMUM 20 10000 4 MIN. MAX. UNITS 0 70 °C 4.75 5.25 ...

Page 5

... Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption CC section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 3160 Figure 2. Test Load GND to 3.0V ≤ ≤ 1.5V 1.5V ...

Page 6

... Specifications ispLSI 3160 ...

Page 7

... Specifications ispLSI 3160 — — ...

Page 8

... Specifications ispLSI 3160 — — ...

Page 9

... Clock (max) + Reg co + Output iobp + grp + ptck(max (#24 + #30 + #43) + (#39) + (#44 + #46) 10.1ns = (0.8 + 1.8 + 3.6) + (1.1) + (1.2 + 1.6) Note: Calculations are based upon timing specifications for the ispLSI 3160-125L. Specifications ispLSI 3160 GLB Feedback # Bypass GLB Reg Bypass #32 # GLB Reg XOR Delays Delay ...

Page 10

... These values are for estimates only. Since the value sensitive to operating conditions and the program in the device, the actual I CC should be verified. Package Thermal Characteristics For the ispLSI 3160-125LB272 strongly recom- mended that the actual Icc be verified to ensure that the maximum junction temperature (T ...

Page 11

... VCC 14, 39, 58, 80, 99, 118, 143, 162, 181, 203 D6, D11, D15, F4, F17, K4, L17, R4, R17, U6, U10, U15 1 NC 76, 77, 79, 81, 180, 182, 184 1. NC pins are not to be connected to any active signals, VCC or GND. Specifications ispLSI 3160 Description 272-Ball BGA J19, J18 M3 M1 ...

Page 12

... V6 I/O 58 102 I I/O 59 103 I I/O 60 105 I I/O 61 106 I I/O 62 107 I I/O 63 108 Specifications ispLSI 3160 Signal PQFP BGA Signal W8 I/O 64 109 T18 I I/O 65 110 T19 I I/O 66 111 T20 I I/O 67 112 R18 I I/O 68 113 P17 I/O 100 158 ...

Page 13

... Pin Configuration ispLSI 3160 208-Pin PQFP (with Heat Spreader) Pinout Diagram 1 I/O 140 2 I/O 141 3 I/O 142 4 I/O 143 5 I/O 144 6 I/O 145 7 I/O 146 8 I/O 147 I/O 148 9 I/O 149 10 GND 11 12 I/O 150 13 I/O 151 14 VCC 15 I/O 152 16 I/O 153 17 I/O 154 18 I/O 155 I/O 156 19 I/O 157 20 I/O 158 21 22 I/O 159 23 TMS/MODE 24 TCK/SCLK 25 TDI/SDI 26 GND 27 BSCAN/ispEN 28 RESET ...

Page 14

... Signal Configuration ispLSI 3160 272-Ball BGA Signal Diagram I/O I/O I/O I 102 103 104 108 I I 107 I/O 94 I/O 97 I/O 99 I/O I 100 105 I/O D I/O 91 I/O 93 I/O 96 GND VCC 101 E I/O 88 I/O 90 I VCC G I/O 84 I/O 85 I/O 87 I/O 89 ...

Page 15

... Specifications ispLSI 3160 3160 – XXX X XXXX X COMMERCIAL ORDERING NUMBER ispLSI 3160-125LQ ispLSI 3160-125LB272 ispLSI 3160-100LQ ispLSI 3160-100LB272 ispLSI 3160-70LQ ispLSI 3160-70LB272 15 Grade Blank = Commercial Package Q = PQFP (with Heat Spreader) B272 = BGA Power L = Low 0212B/3160 PACKAGE 208-Pin PQFP ...

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