MAX146ACPP Maxim Integrated, MAX146ACPP Datasheet - Page 13

• Manufacturer Part Number: MAX146ACPP
• Description: Analog to Digital Converters - ADC Integrated Circuits (ICs)
• Manufacturer: Maxim Integrated

Specifications of MAX146ACPP

• Number Of Channels: 8/4
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: 4-Wire (SPI, Microwire, QSPI, TMS320)
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Package / Case: PDIP N
• Maximum Power Dissipation: 889 mW
• Minimum Operating Temperature: 0 C
• Number Of Converters: 1
• Factory Pack Quantity: 18
• Voltage Reference: Internal 2.5 V or External

In external clock mode, the external clock not only shifts
data in and out, but it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock
period after the last bit of the control byte. Succes-
sive-approximation bit decisions are made and appear
at DOUT on each of the next 12 SCLK falling edges
(Figure 6). SSTRB and DOUT go into a high-impedance
state when CS goes high; after the next CS falling edge,
SSTRB outputs a logic low. Figure 8 shows the SSTRB
timing in external clock mode.
Figure 7. Detailed Serial-Interface Timing
Figure 8. External Clock Mode SSTRB Detailed Timing
SSTRB
SCLK
DOUT
SCLK
CS
DIN
CS
t
CSH
______________________________________________________________________________________
t
DV
t
CSS
t
DS
t
SDV
t
DH
•
• • •
• • •
• • •
External Clock
t
CL
+2.7V, Low-Power, 8-Channel,
PD0 CLOCKED IN
t
CH
• • •
• • •
• • •
• • •
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial clock frequency is less than 100kHz, or if
serial clock interruptions could cause the conversion
interval to exceed 120µs.
In internal clock mode, the MAX146/MAX147 generate
their own conversion clocks internally. This frees the µP
from the burden of running the SAR conversion clock
and allows the conversion results to be read back at the
t
SSTRB
Serial 12-Bit ADCs
t
DO
• • •
t
SSTRB
• • • •
• • •
t
CSH
t
TR
Internal Clock
t
STR
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