MAX1363EUB-T Maxim Integrated, MAX1363EUB-T Datasheet - Page 6

• Manufacturer Part Number: MAX1363EUB-T
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1363EUB-T

• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Input Type: Single-Ended/Differential
• Snr: Yes
• Interface Type: I2C, Serial
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: uMAX
• Maximum Power Dissipation: 444.4 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 4.096 V

4-Channel, 12-Bit System Monitors with Programmable
Trip Window and SMBus Alert Response
ELECTRICAL CHARACTERISTICS (continued)
(V
0.1µF, f
Note 1: Devices configured for unipolar single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain and offset have
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.
Note 5: The throughput rate of the I
Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7: The absolute input-voltage range for the analog inputs (AIN0–AIN3) is from GND to V
Note 8: When the internal reference is configured to be available at AIN3/REF (SEL[2:1] = 11), decouple AIN3/REF to GND with a
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µV
Note 10: Maximum conversion throughput in internal clock mode when the data is not clocked out.
Note 11: For the MAX1363, PSRR is measured as
Note 12: C
Note 13: f
Note 14: A master device must provide a data hold time for SDA (referred to V
(V
T
6
A
DD
DD
= +25°C, unless otherwise noted.)
_______________________________________________________________________________________
-0.4
-0.5
-0.2
-0.3
-0.1
0.5
0.4
0.3
0.2
0.1
= 2.7V to 3.6V (MAX1363), V
= 3.3V (MAX1363), V
0
SCL
0
been calibrated.
Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode.
in monitor mode when not reading back results on the I
0.01µF capacitor.
and for the MAX1364, PSRR is measured as
falling edge.
SCLH
500
= 1.7MHz, T
B
DIFFERENTIAL NONLINEARITY
= total capacitance of one bus line in pF.
1000 1500
must meet the minimum clock low time plus the rise/fall times.
DIGITAL OUTPUT CODE
vs. DIGITAL CODE
⎡
⎢
⎢
⎣
⎡
⎢
⎢
⎣
[
[
V
V
FS
FS
2000 2500 3000 3500
( .
( .
A
5 5
3 6
= T
V
V
( .
( .
)
)
DD
MIN
5 5
3 6
−
−
V
V
V
V
FS
= 5V (MAX1364), f
FS
to T
−
−
( .
( .
DD
4 5
2 7
4 5
2 7
MAX
.
.
2
C bus is limited to 94.4ksps. The MAX1363/MAX1364 can perform conversions up to 133ksps
4000
V
V
V
V
= 4.5V to 5.5V (MAX1364), V
)
)
)
)
, unless otherwise noted. Typical values are at T
]
]
×
×
2
2
V
V
N
N
REF
REF
−
−
-0.2
-0.4
-0.6
-0.8
-1.0
1
1
1.0
0.8
0.6
0.4
0.2
⎤
⎥
⎥
⎦
⎤
⎥
⎥
⎦
0
SCL
0
500
= 1.7MHz, external clock, f
INTEGRAL NONLINEARITY
1000 1500
DIGITAL OUTPUT CODE
vs. DIGITAL CODE
2
C bus.
2000 2500 3000 3500
REF
Typical Operating Characteristics
= 2.048V (MAX1363), V
IL
of SCL) to bridge the undefined region of SCL’s
P-P
4000
.
SAMPLE
A
= +25°C.)
-100
-120
-140
-160
-180
-60
-80
DD
= 94.4ksps, single-ended, unipolar,
0
.
REF
f
f
SAMPLE
IN
= 10kHz
= 4.096V (MAX1364), C
10
= 94.4ksps
FREQUENCY (kHz)
FFT PLOT
20
30
40
REF
50
=