MAX1322ECM Maxim Integrated, MAX1322ECM Datasheet - Page 12

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MAX1322ECM

Manufacturer Part Number
MAX1322ECM
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX1322ECM

Number Of Channels
2
Architecture
SAR
Conversion Rate
526 KSPs
Resolution
14 bit
Input Type
Single-Ended
Snr
76 dB
Interface Type
Parallel
Operating Supply Voltage
2.7 V to 5.25 V, 4.75 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Package / Case
LQFP-48
Maximum Power Dissipation
1818 mW
Minimum Operating Temperature
- 40 C
Number Of Converters
1
Voltage Reference
2.5 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MAX1322ECM+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
MAX1322ECM+T
Manufacturer:
Maxim Integrated
Quantity:
10 000
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
12
MAX1316
MAX1320
MAX1324
______________________________________________________________________________________
41
42
43
44
45
46
47
48
MAX1317
MAX1321
MAX1325
9–12
PIN
41
42
43
44
45
46
47
48
MAX1318
MAX1322
MAX1326
7–12
41
42
43
44
45
46
47
48
CONVST
ALLON
NAME
SHDN
EOLC
CLK
WR
I.C.
RD
CS
End-of-Last-Conversion Output. EOLC goes low to indicate the end
of the last conversion. EOLC returns high when CONVST goes low
for the next conversion sequence.
Read Input. When RD and CS go low, the device initiates a read
command of the parallel data buses, D0–D13. D0–D13 are high
impedance while either RD or CS is high.
Write Input. The write command initiates when WR and CS go low. A
write command loads the configuration byte on D0–D7.
Chip-Select Input. Pulling CS low activates the digital interface.
D0–D13 are high impedance while either CS or RD is high.
Convert-Start Input. Driving CONVST high places the device in hold
mode and initiates the conversion process. The analog inputs are
sampled on the rising edge of CONVST. When CONVST is low, the
analog inputs are tracked.
External-Clock Input. CLK accepts an external-clock signal up to
15MHz. Connect CLK to DGND for internally clocked conversions.
To select external-clock mode, set INTCLK/EXTCLK = 0.
Shutdown Input. Set SHDN = 0 for normal operation. Set SHDN = 1
for shutdown mode.
Enable-All-Channels Input. Drive ALLON high to enable all input
channels. When ALLON is low, only input channels selected as
active are powered. Select channels as active using the
configuration register.
Internally Connected. Connect I.C. to AGND. For factory use only.
Pin Description (continued)
FUNCTION

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