MAX1322ECM Maxim Integrated, MAX1322ECM Datasheet - Page 15

• Manufacturer Part Number: MAX1322ECM
• Description: Analog to Digital Converters - ADC
• Manufacturer: Maxim Integrated

Specifications of MAX1322ECM

• Number Of Channels: 2
• Architecture: SAR
• Conversion Rate: 526 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 76 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-48
• Maximum Power Dissipation: 1818 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 2.5 V

These devices provide an internal clock of 10MHz
(typ). Alternatively, an external clock can be used.
Internal-clock mode frees the microprocessor from the
burden of running the ADC conversion clock. For internal-
clock operation, connect INTCLK/EXTCLK to AV
connect CLK to DGND. Table 1 illustrates the total con-
version time using internal-clock mode.
For external-clock operation, connect INTCLK/EXTCLK
to AGND and connect an external-clock source to CLK.
Note that INTCLK/EXTCLK is referenced to the analog
power supply, AV
be up to 15MHz, with a duty cycle between 30% and
70%. Clock frequencies of 100kHz and lower can be
used, but the droop in the T/H circuits reduce linearity.
Most applications require an input buffer to achieve 14-
bit accuracy. Although slew-rate and bandwidth are
important, the most critical specification is settling time.
The sampling requires a relatively brief sampling inter-
val of 150ns. At the beginning of the acquisition, the
internal sampling capacitor array connects to CH_ (the
amplifier output), causing some output disturbance.
Ensure the amplifier is capable of settling to at least 14-
bit accuracy during this interval. Use a low-noise, low-
distortion, wideband amplifier (such as the MAX4350 or
Figure 3. Software Channel Wake-Up Timing (ALLON = 0)
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
CONVST
D0–D7
EOLC
EOC
CLK
WR
DD
______________________________________________________________________________________
. The external-clock frequency can
Selecting an Input Buffer
DATA-IN
LATCH
DATA-IN CHANGES ONE OR MORE CHANNELS
FROM POWER-DOWN TO ACTIVE MODE
t
ACQ
Clock Modes
External Clock
Internal Clock
1
DUMMY
CONVERSION
START
DD
2
and
3
MAX4265), which settles quickly and is stable with the
ADC’s capacitive load (in parallel with any bypass
capacitors on the analog inputs).
The bidirectional, parallel, digital interface sets the 8-bit
configuration register (see the Configuration Register
section) and outputs the 14-bit conversion result. The
interface includes the following control signals: chip
select (CS), read (RD), write (WR), end of conversion
(EOC), end of last conversion (EOLC), convert start
(CONVST), shutdown (SHDN), all on (ALLON), internal-
clock select (INTCLK /EXTCLK), and external-clock input
(CLK). Figures 4, 5, 6, 7, Table 4, and the Timing
Characteristics section show the operation of the inter-
face. D0–D7 are bidirectional, and D8–D13 are output
only. All bits are high impedance when RD = 1 or CS = 1.
Enable channels as active by writing to the configuration
register through I/O lines D0–D7 (Table 2). The bits in the
configuration register map directly to the channels, with
D0 controlling channel zero, and D7 controlling channel
seven. Setting any bit high activates the corresponding
input channel, while resetting any bit low deactivates the
corresponding channel. Devices with fewer than eight
channels contain some bits that have no function.
>14 CYCLES
4
5
CONVERSION
ACTUAL
14
START
Applications Section
Configuration Register
15
t
ACQ
Digital Interface
1
SAMPLE
15