MAX148BMJP Maxim Integrated, MAX148BMJP Datasheet - Page 12

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MAX148BMJP

Manufacturer Part Number
MAX148BMJP
Description
Analog to Digital Converters - ADC
Manufacturer
Maxim Integrated
Datasheet

Specifications of MAX148BMJP

Number Of Channels
8/4
Architecture
SAR
Conversion Rate
133 KSPs
Resolution
10 bit
Input Type
Single-Ended/Differential
Snr
Yes
Interface Type
4-Wire, Microwire, QSPI, Serial, SPI
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Package / Case
CDIP N
Maximum Power Dissipation
640 mW
Minimum Operating Temperature
- 55 C
Number Of Converters
1
Voltage Reference
External
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
The T/H acquires the input signal as the last three bits of
the control byte are clocked into DIN. Bits PD1 and PD0
of the control byte program the clock mode. Figures 7–10
show the timing characteristics common to both modes.
In external clock mode, the external clock not only shifts
data in and out, but it also drives the analog-to-digital
conversion steps. SSTRB pulses high for one clock period
after the last bit of the control byte. Successive- approxi-
mation bit decisions are made and appear at DOUT on
each of the next 12 SCLK falling edges (Figure 6). SSTRB
Figure 7. Detailed Serial-Interface Timing
Figure 8. External Clock Mode SSTRB Detailed Timing
12
DOUT
SCLK
DIN
CS
SSRTB
SCLK
CS
t
CSH
t
DV
t
CSS
t
DS
t
DH
t
SDV
External Clock
t
CL
PD0 CLOCKED IN
t
CH
and DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic-low. Figure 8 shows the SSTRB timing in external
clock mode.
The conversion must complete in some minimum time, or
droop on the sample-and-hold capacitors may degrade
conversion results. Use internal clock mode if the serial-
clock frequency is less than 100kHz, or if serial-clock
interruptions could cause the conversion interval to
exceed 120Fs.
t
SSTRB
t
DO
t
SSTRB
t
CSH
t
TR
t
STR

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