AT89LP51ED2-20JU Atmel, AT89LP51ED2-20JU Datasheet - Page 57

• Manufacturer Part Number: AT89LP51ED2-20JU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20JU

• Rohs: yes
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: PLCC-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 27

8. Power Saving Modes
8.1
Table 8-1.
3714A–MICRO–7/11
Symbol
SMOD1
SMOD0
PWDEX
POF
GF1, GF0
PD
IDL
PCON = 87H
Not Bit Addressable
Bit
Idle Mode
Function
Double Baud Rate bit. Doubles the baud rate of the UART in Modes 1, 2, or 3.
Frame Error Select. When SMOD0 = 1, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after
a frame error regardless of the state of SMOD0.
Power-down Exit Mode. When PWDEX = 0, wake up from Power-down is externally controlled. When PWDEX = 1, wake
up from Power-down is internally timed.
Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not
affected by RST or BOD (i.e. warm resets).
General-purpose Flags
Power-down bit. Setting this bit activates power-down operation. The PD bit is cleared automatically by hardware when
waking up from power-down.
Idle Mode bit. Setting this bit activates Idle mode operation. The IDL bit is cleared automatically by hardware when
waking up from idle
PCON
SMOD1
7
– Power Control Register
The AT89LP51RD2/ED2/ID2 supports two different software selectable power-reducing modes:
Idle and Power-down. These modes are accessed through the PCON register. Additional steps
may be required to achieve the lowest possible power consumption while using these modes. In
addition the AT89LP51RD2/ED2/ID2 has fusible configuration options that can further reduce
the active power consumption under certain circumstances.
Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU
state is preserved in its entirety, including the RAM, stack pointer, program counter, program
status word, and accumulator. The Port pins hold the logic states they had at the time that Idle
was activated. Idle mode leaves the peripherals running in order to allow them to wake up the
CPU when an interrupt is generated. The timer and UART peripherals continue to function dur-
ing Idle. If these functions are not needed during idle, they should be explicitly disabled by
clearing the appropriate control bits in their respective SFRs. The watchdog may be selectively
enabled or disabled during Idle by setting/clearing the WDIDLE bit. The Brown-out Detector is
always active during Idle. Any enabled interrupt source or reset may terminate Idle mode. When
exiting Idle mode with an interrupt, the interrupt will immediately be serviced, and following RETI
the next instruction to be executed will be the one following the instruction that put the device
into Idle.
The power consumption during Idle mode can be further reduced by prescaling down the system
clock using the System Clock Prescaler
divider will affect all peripheral functions and baud rates may need to be adjusted to maintain
their rate with the new clock frequency.
.
SMOD0
6
PWDEX
5
AT89LP51RD2/ED2/ID2 Preliminary
POF
4
GF1
(Section 6.8 on page
3
GF0
2
Reset Value = 000X 0000B
49). Be aware that the clock
PD
1
IDL
0
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