LFE3-150EA-9FN672C Lattice, LFE3-150EA-9FN672C Datasheet - Page 100

• Manufacturer Part Number: LFE3-150EA-9FN672C
• Description: FPGA - Field Programmable Gate Array 149K LUTs 380 I/O 1.2V -9 SPEED
• Manufacturer: Lattice

Specifications of LFE3-150EA-9FN672C

• Rohs: yes
• Number Of Gates: 149 K
• Number Of Logic Blocks: 372
• Embedded Block Ram - Ebr: 6850 Kbit
• Number Of I/os: 380
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: FPBGA-672
• Distributed Ram: 303 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 370.9 mA
• Factory Pack Quantity: 40

Serial Rapid I/O Type 2/CPRI LV E.24 Electrical and Timing Characteristics
AC and DC Characteristics
Table 3-15. Transmit
Table 3-16. Receive and Jitter Tolerance
T
Z
J
J
1. Rise and Fall times measured with board trace, connector and approximately 2.5pf load.
2. Total jitter includes both deterministic jitter and random jitter. The random jitter is the total jitter minus the actual deterministic jitter.
3. Jitter values are measured with each CML output AC coupled into a 50-ohm impedance (100-ohm differential impedance).
4. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal.
5. Values are measured at 2.5 Gbps.
RL
RL
Z
J
J
J
J
T
1. Total jitter includes deterministic jitter, random jitter and sinusoidal jitter. The sinusoidal jitter tolerance mask is shown in Figure 3-18.
2. Jitter values are measured with each high-speed input AC coupled into a 50-ohm impedance.
3. Jitter and skew are specified between differential crossings of the 50% threshold of the reference signal.
4. Jitter tolerance, Differential Input Sensitivity and Receiver Eye Opening parameters are characterized when Full Rx Equalization is enabled.
5. Values are measured at 2.5 Gbps.
TX_DDJ
TX_TJ
RX_DJ
RX_RJ
RX_SJ
RX_TJ
RF
TX_DIFF_DC
RX_DIFF
RX_EYE
RX_DIFF
RX_CM
Symbol
1
Symbol
2, 3, 4, 5
2, 3, 4, 5
1, 2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
3, 4, 5
Differential return loss
Common mode return loss
Differential termination resistance
Deterministic jitter tolerance (peak-to-peak)
Random jitter tolerance (peak-to-peak)
Sinusoidal jitter tolerance (peak-to-peak)
Total jitter tolerance (peak-to-peak)
Receiver eye opening
Differential rise/fall time
Differential impedance
Output data deterministic jitter
Total output data jitter
Description
Description
3-47
Test Conditions
From 100 MHz to 2.5 GHz
From 100 MHz to 2.5 GHz
20%-80%
Test Conditions
DC and Switching Characteristics
LatticeECP3 Family Data Sheet
Min.
—
80
—
—
Min.
0.35
10
80
—
—
—
—
6
Typ.
100
80
—
—
Typ.
100
—
—
—
—
—
—
—
Max.
0.17
0.35
120
—
Max.
0.37
0.18
0.10
0.65
120
—
—
—
Ohms
Units
Ohms
Units
ps
UI
UI
dB
dB
UI
UI
UI
UI
UI