LCMXO2-1200ZE-1MG132C Lattice, LCMXO2-1200ZE-1MG132C Datasheet - Page 60

no-image

LCMXO2-1200ZE-1MG132C

Manufacturer Part Number
LCMXO2-1200ZE-1MG132C
Description
FPGA - Field Programmable Gate Array 1280 LUTs 105 I/O 1.2V -1 SPD
Manufacturer
Lattice
Datasheet

Specifications of LCMXO2-1200ZE-1MG132C

Rohs
yes
Number Of Gates
1.2 K
Embedded Block Ram - Ebr
64 Kbit
Number Of I/os
105
Maximum Operating Frequency
104 MHz
Operating Supply Voltage
1.14 V to 3.465 V, 2.375 V to 3.465 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
csBGA-132
Distributed Ram
10 Kbit
Minimum Operating Temperature
0 C
Operating Supply Current
56 uA
Factory Pack Quantity
360
User Flash Memory - Ufm
64 Kbit

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LCMXO2-1200ZE-1MG132C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LCMXO2-1200ZE-1MG132CR1
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Generic DDRX2 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Centered
t
t
f
f
f
Generic DDRX4 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Aligned
t
t
f
f
f
Generic DDRX4 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Centered
t
t
f
f
f
7:1 LVDS Outputs – GDDR71_TX.ECLK.7:1
t
t
f
f
f
DVB
DVA
DATA
DDRX2
SCLK
DIA
DIB
DATA
DDRX4
SCLK
DVB
DVA
DATA
DDRX4
SCLK
DVB
DVA
DATA
DDR71
CLKOUT
Parameter
Output Data Valid Before CLK
Output
Output Data Valid After CLK
Output
DDRX2 Serial Output Data
Speed
DDRX2 ECLK Frequency
(minimum limited by PLL)
SCLK Frequency
Output Data Invalid After CLK
Output
Output Data Invalid Before
CLK Output
DDRX4 Serial Output Data
Speed
DDRX4 ECLK Frequency
SCLK Frequency
Output Data Valid Before CLK
Output
Output Data Valid After CLK
Output
DDRX4 Serial Output Data
Speed
DDRX4 ECLK Frequency
(minimum limited by PLL)
SCLK Frequency
Output Data Valid Before CLK
Output
Output Data Valid After CLK
Output
DDR71 Serial Output Data
Speed
DDR71 ECLK Frequency
7:1 Output Clock Frequency
(SCLK) (minimum limited by
PLL)
Description
9
MachXO2-640U,
MachXO2-1200/U and
larger devices, top side
only
MachXO2-640U,
MachXO2-1200/U and
larger devices, top side
only
MachXO2-640U,
MachXO2-1200/U and
larger devices, top side
only
MachXO2-640U,
MachXO2-1200/U and
larger devices, top side
only.
Device
3-21
0.535
0.535
0.455
0.455
Min.
-6
DC and Switching Characteristics
0.200
0.200
0.160
0.160
Max.
664
332
166
756
378
756
378
756
378
108
95
95
MachXO2 Family Data Sheet
0.670
0.670
0.570
0.570
Min.
-5
0.215
0.215
0.180
0.180
Max.
554
277
139
630
315
630
315
630
315
79
79
90
0.830
0.830
0.710
0.710
Min.
-4
0.230
0.230
0.200
0.200
Max.
462
524
262
524
524
262
231
116
262
66
66
75
Units
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
9
9
9

Related parts for LCMXO2-1200ZE-1MG132C