LCMXO2-2000HC-6TG100I Lattice, LCMXO2-2000HC-6TG100I Datasheet - Page 8

• Manufacturer Part Number: LCMXO2-2000HC-6TG100I
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 80 IO 3.3V 6 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-6TG100I

• Rohs: yes
• Maximum Operating Frequency: 133 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-100
• Minimum Operating Temperature: - 40 C
• Operating Supply Current: 82 uA
• Factory Pack Quantity: 90

Table 2-2. Slice Signal Descriptions
Modes of Operation
Each slice has up to four potential modes of operation: Logic, Ripple, RAM and ROM.
Logic Mode
In this mode, the LUTs in each slice are configured as 4-input combinatorial lookup tables. A LUT4 can have 16
possible input combinations. Any four input logic functions can be generated by programming this lookup table.
Since there are two LUT4s per slice, a LUT5 can be constructed within one slice. Larger look-up tables such as
LUT6, LUT7 and LUT8 can be constructed by concatenating other slices. Note LUT8 requires more than four
slices.
Ripple Mode
Ripple mode supports the efficient implementation of small arithmetic functions. In Ripple mode, the following func-
tions can be implemented by each slice:
• Addition 2-bit
• Subtraction 2-bit
• Add/subtract 2-bit using dynamic control
• Up counter 2-bit
• Down counter 2-bit
• Up/down counter with asynchronous clear
• Up/down counter with preload (sync)
• Ripple mode multiplier building block
• Multiplier support
• Comparator functions of A and B inputs
– A greater-than-or-equal-to B
– A not-equal-to B
– A less-than-or-equal-to B
1. See Figure 2-3 for connection details.
2. Requires two PFUs.
Function
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Inter-PFU signal
Inter-PFU signal
Multi-purpose
Control signal
Control signal
Control signal
Data signals
Data signals
Data signals
Data signals
Data signal
Data signal
Type
Signal Names
A0, B0, C0, D0 Inputs to LUT4
A1, B1, C1, D1 Inputs to LUT4
Q0, Q1
M0/M1
F0, F1
OFX0
OFX1
FCIN
FCO
LSR
CLK
CE
Multi-purpose input
Clock enable
Local set/reset
System clock
Fast carry in
LUT4 output register bypass signals
Register outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT8
Fast carry out
2-4
1
1
Description
MachXO2 Family Data Sheet
2
MUX depending on the slice
Architecture