iCE40LP640-CM81 Lattice, iCE40LP640-CM81 Datasheet
iCE40LP640-CM81
Specifications of iCE40LP640-CM81
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iCE40LP640-CM81 Summary of contents
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... QN84 packall chip-scale BGA Note 1: At 1.2V VCC Note 2: No PLL Available Note 3: Only 1 PLL Available © 2007-2012 by Lattice Semiconductor Corporation. All rights reserved. www.latticesemi.com Figure 1: iCE40 LP-Series Family Architectural Features 35 µ kHz (Typical) I/O Bank 0 Programmable Interconnect ...
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... See the separate iCE40 Pinout Excel files for package and pinout specifications. Figure 2: iCE40LP 225 Low Power Series Logic Cells 640, 1K, 4K, 8K Lattice Semiconductor Corporation www.latticesemi.com iCE40P Ordering Codes (packaged, non-die components iCE40LP8K-CM225 225-ball Chip-Scale BGA Package (7x7 mm footprint, 0.4 mm pitch) ™ ...
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... VPP_FAST, used only for fast production programming, must be left floating or unconnected in application, except CM36 and CM49 packages MUST have VPP_FAST ball connected to VCCIO_0 ball externally. 3. VCCPLL must be tied to VCC when PLL is not used. Lattice Semiconductor Corporation www.latticesemi.com ™ Table 2 may cause permanent damage to the device. These are stress ratings only; ...
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... NOTE: All characteristics are characterized and may or may not be tested on each pin on each device. Single-ended I/O Characteristics Nominal I/O Bank Supply I/O Standard Voltage LVCMOS33 3.3V LVCMOS25 2.5V LVCMOS18 1.8V LVCMOS15 1.5V Lattice Semiconductor Corporation www.latticesemi.com ™ Family Table 4: PIO Pin Electrical Characteristics Conditions Minimum V = VCCIO max V ...
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... Differential output voltage: Table 7: Recommended Operating Conditions for Differential Outputs VCCIO_x (V) I/O Min Nom Max Standard LVDS 2.38 2.50 2.63 SubLVDS 1.71 1.80 1.89 Lattice Semiconductor Corporation www.latticesemi.com Figure 3: Differential Input Specifications Differential input voltage ICM GND Recommended Operating Conditions for Differential Inputs V (mV) ID Min Nom Max ...
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... The following examples provide some guidelines of device performance. The actual performance depends on the specific application and how it is physically implemented in the iCE65P FPGA using the Lattice iCEcube2 software. The following guidelines assume typical conditions (VCC = 1 1 specified, temperature = 25 ˚C). Apply derating factors using the iCEcube2 timing analyzer to adjust to other operating regimes ...
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... Inter- PIO Asynchronous delay from adjacent interconnect to PIO output PADO connect pad including interconnect delay. output Lattice Semiconductor Corporation www.latticesemi.com ™ The timing shown is for the LVCMOS25 I/O standard in all I/O banks. The Programmable I/O (PIO) Pad-to-Pad Timing Circuit PAD PIO Programmable I/O (PIO) Sequential Timing Circuit ...
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... Write clock High time RMWCKH RCLK RCLK t Write clock Low time RMWCKL t Write clock cycle time RMWCYC F Sustained write clock frequency WMAX Lattice Semiconductor Corporation www.latticesemi.com Figure 9: RAM4K Timing Circuit PIO WDATA RAM4K RAM Block (256x16) WCLK Table 10: Typical RAM4K Block Timing Description ™ ...
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... Minimum reset pulse width RST Notes: 1. Output jitter performance is affected by input jitter. A clean reference clock < 100ps jitter must be used to ensure best jitter performance. 2. The output jitter specification refers to the intrinsic jitter of the PLL. Lattice Semiconductor Corporation www.latticesemi.com Figure 10: Phase-Locked Loop (PLL) PLL LATCHINPUTVALUE DYNAMICDELAY[3:0] ...
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... Supported by some high-speed SPI serial Flash PROMs 0 0 Oscillator turned off by default after configuration to save power. Table 12 and the maximum configuration bitstream size from Device Default iCE40LP640 iCE40LP1K iCE40LP4K 230 iCE40LP8K 230 Table 14: General Configuration Timing Description Minimum CRESET_B Low pulse width required to restart ...
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... NOTE: The typical static current for I/O Banks and the SPI bank is less than the accuracy of the device tester. Power Estimator To estimate the power consumption for a specific application, please download and use the iCE40LP Power Estimator Spreadsheet or use the power estimator built into the iCEcube2 software. Lattice Semiconductor Corporation www.latticesemi.com iCE40LP640 iCE40LP1K VCC Typical Typical 1.2V ...
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... Initial Release © 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...