LCMXO2-256ZE-1SG32I Lattice, LCMXO2-256ZE-1SG32I Datasheet - Page 31

• Manufacturer Part Number: LCMXO2-256ZE-1SG32I
• Description: FPGA - Field Programmable Gate Array 256 LUTs 22 I/O 1.2V -1 Speed
• Manufacturer: Lattice

Specifications of LCMXO2-256ZE-1SG32I

• Rohs: yes
• Number Of Gates: 256
• Embedded Block Ram - Ebr: 0 Kbit
• Number Of I/os: 22
• Maximum Operating Frequency: 104 MHz
• Operating Supply Voltage: 1.14 V to 1.26 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Distributed Ram: 2 Kbit
• Operating Supply Current: 18 uA
• Factory Pack Quantity: 490

Hot Socketing
The MachXO2 devices have been carefully designed to ensure predictable behavior during power-up and power-
down. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of
the system. These capabilities make the MachXO2 ideal for many multiple power supply and hot-swap applica-
tions.
On-chip Oscillator
Every MachXO2 device has an internal CMOS oscillator. The oscillator output can be routed as a clock to the clock
tree or as a reference clock to the sysCLOCK PLL using general routing resources. The oscillator frequency can be
divided by internal logic. There is a dedicated programming bit and a user input to enable/disable the oscillator. The
oscillator frequency ranges from 2.08 MHz to 133 MHz. The software default value of the Master Clock (MCLK) is
nominally 2.08 MHz. When a different MCLK is selected during the design process, the following sequence takes
place:
1. Device powers up with a nominal MCLK frequency of 2.08 MHz.
2. During configuration, users select a different master clock frequency.
3. The MCLK frequency changes to the selected frequency once the clock configuration bits are received.
4. If the user does not select a master clock frequency, then the configuration bitstream defaults to the MCLK fre-
Table 2-14 lists all the available MCLK frequencies.
Table 2-14. Available MCLK Frequencies
Embedded Hardened IP Functions and User Flash Memory
All MachXO2 devices provide embedded hardened functions such as SPI, I
and higher density devices also provide User Flash Memory (UFM). These embedded blocks interface through the
WISHBONE interface with routing as shown in Figure 2-20.
quency of 2.08 MHz.
MCLK (MHz, Nominal)
2.08 (default)
2.46
3.17
4.29
5.54
8.31
7
MCLK (MHz, Nominal)
2-27
10.23
14.78
20.46
29.56
9.17
13.3
26.6
2
C and Timer/Counter. MachXO2-640/U
MachXO2 Family Data Sheet
MCLK (MHz, Nominal)
33.25
44.33
88.67
53.2
66.5
133
38
Architecture