iCE65L01F-LCB132C Lattice, iCE65L01F-LCB132C Datasheet - Page 98

• Manufacturer Part Number: iCE65L01F-LCB132C
• Description: FPGA - Field Programmable Gate Array iCE65 1280 LUTs, 1.0 1.2V Ultra Low-Power
• Manufacturer: Lattice

Specifications of iCE65L01F-LCB132C

• Rohs: yes
• Number Of Gates: 1280
• Number Of Logic Blocks: 16
• Number Of I/os: 93
• Maximum Operating Frequency: 256 MHz
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: CBGA-132
• Distributed Ram: 64 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 12 uA
• Factory Pack Quantity: 384

iCE65 Ultra Low-Power mobileFPGA
Electrical Characteristics
(2.42, 30-MAR-2012)
98
Absolute Maximum Ratings
Recommended Operating Conditions
All parameter limits are specified under worst-case supply voltage, temperature, and processing conditions.
Stresses beyond those listed under
only; functional operation of the device at these or any other conditions beyond those listed under the
Recommended Operating Conditions is not implied. Exposure to absolute maximum conditions for extended
periods of time adversely affects device reliability.
NOTE:
VPP_FAST is only used for fast production programming. Leave floating or unconnected in application. When the iCE65
device is active, VPP_2V5 must be connected to a valid voltage.
VIN_VREF
VPP_FAST
VPP_FAST
VPP_2V5
VCCIO_0
VCCIO_1
VCCIO_2
VCCIO_3
SPI_VCC
VIN_SPI
VPP_2V5
VCCIO_0
VCCIO_1
VCCIO_2
VCCIO_3
VCCIO_3
SPI_VCC
SPI_VCC
Symbol
Symbol
VIN_0
VIN_1
VIN_2
VIN_3
T
IOUT
VCC
VCC
T
PROG
T
T
STG
A
J
Core supply voltage
VPP_2V5 NVCM
programming and operating
supply
Optional fast NVCM programming supply
SPI interface supply voltage
I/O standards, all banks*
I/O standards only available
in iCE65L04/08 I/O Bank 3*
Ambient temperature
NVCM programming temperature
Core supply Voltage
VPP_2V5 NVCM programming and operating supply
Optional fast NVCM programming supply
I/O bank supply voltage (I/O Banks 0, 1, and 2 plus SPI
interface)
I/O Bank 3 supply voltage
Voltage applied to PIO pin within a specific I/O bank (I/O
Banks 0, 1, and 2 plus SPI interface)
Voltage applied to PIO pin within I/O Bank 3
DC output current per pin
Junction temperature
Storage temperature, no bias
Table 48:
Table 47: Absolute Maximum Ratings
Table 47
Description
Description
Recommended Operating Conditions
–L: Ultra-Low Power mode
–L: Low Power
–T: High Performance
Release from Power-on Reset
Configure from NVCM
NVCM programming
LVCMOS33
Non-standard voltage:
in between 2.5V and 3.3V
use LVCMOS25 in iCEcube2
LVCMOS25, LVDS
LVCMOS18, SubLVDS
LVCMOS15
SSTL2
SSTL18
MDDR
Commercial (C)
Industrial (I)
may cause permanent damage to the device. These are stress ratings
™
Family
Minimum
Nominal
0.95
1.14
1.30
2.30
2.30
1.71
3.14
-5%
2.38
1.71
1.43
2.38
1.71
1.71
–40
–0.5
–0.5
–0.5
–1.0
–0.5
10
Min
–55
–65
0
Lattice Semiconductor Corporation
—
Leave unconnected in application
2.5< Nominal
iCE65L04/08: 3.6
iCE65L04/08: 3.6
iCE65L01: 4.00
iCE65L01: 4.00
Nominal
<3.3
1.00
1.20
3.30
2.50
1.80
1.50
2.50
1.80
1.80
25
—
—
—
—
—
—
Max
1.42
4.00
125
150
5.5
20
www.latticesemi.com
Maximum
Nominal
+5%
3.47
3.47
2.63
1.89
1.58
2.63
1.89
1.89
1.05
1.26
3.47
3.47
3.00
70
85
30
Units
mA
°C
°C
V
V
V
V
V
V
V
Units
°C
°C
°C
V
V
V
V
V
V
V
V
V
V
V
V
V
V