GLS36VF1601G-70-4I-L1PE Greenliant, GLS36VF1601G-70-4I-L1PE Datasheet - Page 3

• Manufacturer Part Number: GLS36VF1601G-70-4I-L1PE
• Description: Flash 16M Flash 1M SRAM Industrial Temp
• Manufacturer: Greenliant

Specifications of GLS36VF1601G-70-4I-L1PE

• Rohs: yes
• Memory Type: Flash
• Memory Size: 16 Mbit
• Timing Type: Asynchronous
• Access Time: 70 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 15 mA
• Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: LFBGA-48

16 Mbit Concurrent SuperFlash
GLS36VF1601E / GLS36VF1602E
Program Operation
These devices are programmed on a word-by-word or
byte-by-byte basis depending on the state of the BYTE#
pin. Before programming, one must ensure that the sector
which is being programmed is fully erased.
The Program operation is accomplished in three steps:
See Figures 9 and 10 for WE# and CE# controlled Pro-
gram operation timing diagrams and Figure 24 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during an internal Program opera-
tion are ignored.
©2010 Greenliant Systems, Ltd.
1. Software Data Protection is initiated using the
2. Address and data are loaded.
3. The internal Program operation is initiated after
three-byte load sequence.
During the Program operation, the addresses are
latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever
occurs first.
the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once ini-
tiated, will be completed typically within 7 µs.
3
Sector-Erase/Block-Erase Operation
These devices offer both Sector-Erase and Block-Erase
operations. These operations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis. The
sector architecture is based on a uniform sector size of 2
KWord. The Block-Erase mode is based on a uniform block
size of 32 KWord. The Sector-Erase operation is initiated by
executing a six-byte command sequence with a Sector-
Erase command (30H) and sector address (SA) in the last
bus cycle. The Block-Erase operation is initiated by execut-
ing a six-byte command sequence with Block-Erase com-
mand (50H) and block address (BA) in the last bus cycle.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The inter-
nal Erase operation begins after the sixth WE# pulse. Any
commands issued during the Sector- or Block-Erase opera-
tion are ignored except Erase-Suspend and Erase-
Resume. See Figures 14 and 15 for timing waveforms.
Chip-Erase Operation
The devices provide a Chip-Erase operation, which allows
the user to erase all sectors/blocks to the “1” state. This is
useful when a device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid Read is Toggle Bit or Data# Poll-
ing. Any commands issued during the Chip-Erase opera-
tion are ignored. See Table 6 for the command sequence,
Figure 13 for timing diagram, and Figure 28 for the flow-
chart. When WP# is low, any attempt to Chip-Erase will be
ignored.
S71274-05-000
Data Sheet
05/10