MC100EPT21DG ON Semiconductor, MC100EPT21DG Datasheet

MC100EPT21DG

Manufacturer Part Number

MC100EPT21DG

Description

IC XLATOR LVPECL-LVTTL DFF 8SOIC

Manufacturer

ON Semiconductor

Series

100EPTr

Datasheet

1.MC100EPT21MNR4G.pdf (8 pages)

Specifications of MC100EPT21DG

Logic Function

Translator

Number Of Bits

Input Type

CML, LVDS, LVPECL

Output Type

LVTTL, LVCMOS

Number Of Channels

Number Of Outputs/channel

Differential - Input:output

Yes/No

Propagation Delay (max)

1.8ns

Voltage - Supply

3 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Package / Case

8-SOIC (3.9mm Width)

Supply Voltage

3 V ~ 3.6 V

Logic Type

Translator

Logic Family

ECL

Translation

CML/LVDS/LVPECL to LVCMOS/LVTTL

High Level Output Current

- 3 mA

Low Level Output Current

24 mA

Propagation Delay Time

2.25 ns @ 3 V to 3.6 V

Supply Voltage (max)

3.6 V

Supply Voltage (min)

3 V

Maximum Operating Temperature

+ 85 C

Minimum Operating Temperature

- 40 C

Mounting Style

SMD/SMT

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Data Rate

Lead Free Status / Rohs Status

Lead free / RoHS Compliant

Other names

MC100EPT21DGOS

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

MC100EPT21DG

Manufacturer:

ON/安森美

Quantity:

20 000

Current page: 1 of 8
Download datasheet (128Kb)

MC100EPT21

3.3V Differential

LVPECL/LVDS/CML to

LVTTL/LVCMOS Translator

LVTTL/LVCMOS translator. Because LVPECL (Positive ECL),

LVDS, and positive CML input levels and LVTTL/LVCMOS output

levels are used, only +3.3 V and ground are required. The small

outline 8−lead SOIC package makes the EPT21 ideal for applications

which require the translation of a clock or data signal.

single−ended or differential input mode. When single−ended cap

coupled, V

non−inverting buffer, or V

driven for an inverting buffer. When cap coupled differentially, V

output is connected through a resistor to each input pin. If used, the

additional information see AND8020/D. For a single−ended direct

connection use an external voltage reference source such as a resistor

divider. Do not use V

another device.

Features

•

March, 2010 − Rev. 21

The MC100EPT21 is a Differential LVPECL/LVDS/CML to

The V

1.4 ns Typical Propagation Delay

Maximum Frequency > 275 MHz Typical

LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs

24 mA TTL outputs

Operating Range: V

The 100 Series Contains Temperature Compensation

Pb−Free Packages are Available

pin should be bypassed to V

Output

output allows this EPT21 to be cap coupled in either

output is tied to the D input and D is driven for a

for a single−ended direct connection or port to

= 3.0 V to 3.6 V with GND = 0 V

output is tied to the D input and D is

via a 0.01 mF capacitor. For

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

*For additional marking information, refer to

(Note: Microdot may be in either location)

Application Note AND8002/D.

ORDERING INFORMATION

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

M = Date Code

G = Pb−Free Package

http://onsemi.com

CASE 506AA

CASE 948R

MN SUFFIX

DT SUFFIX

CASE 751

D SUFFIX

TSSOP−8

SO−8

DFN8

Publication Order Number:

MC100EPT21/D

DIAGRAMS*

MARKING

KPT21

ALYWG

ALYW

3RMG

KA21

Related parts for MC100EPT21DG

MC100EPT21DG Summary of contents

Page 1

MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small ...

Page 2

NC 1 LVTTL LVPECL Figure 1. Logic Diagram and 8−Lead Pinout (Top View) Table 2. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite ...

Page 3

Table 4. PECL INPUT DC CHARACTERISTICS Symbol Characteristic V Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Output Voltage Reference BB V Input HIGH Voltage Common Mode IHCMR Range (Differential Configuration) (Note 4) I Input HIGH ...

Page 4

V 2500 2000 1500 1000 500 100 150 200 250 FREQUENCY (MHz) Figure includes L fixture capacitance Figure 3. TTL Output Loading Used For Device Evaluation http://onsemi.com ...

Page 5

... ORDERING INFORMATION Device MC100EPT21D MC100EPT21DG MC100EPT21DR2 MC100EPT21DR2G MC100EPT21DT MC100EPT21DTG MC100EPT21DTR2 MC100EPT21DTR2G MC100EPT21MNR4 MC100EPT21MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D ...

Page 6

... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 7

K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− G SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...

Page 8

... 0.05 C NOTE 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...

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