RSDEC-DBLK-XM-U3 Lattice, RSDEC-DBLK-XM-U3 Datasheet
RSDEC-DBLK-XM-U3
Specifications of RSDEC-DBLK-XM-U3
Related parts for RSDEC-DBLK-XM-U3
RSDEC-DBLK-XM-U3 Summary of contents
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Dynamic Block Reed-Solomon Decoder User’s Guide December 2010 IPUG52_01.6 ...
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... Lattice Technical Support.................................................................................................................................... 31 © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... LatticeSC/M................................................................................................................................................ 32 LatticeXP.................................................................................................................................................... 32 LatticeXP2.................................................................................................................................................. 32 Related Information............................................................................................................................................. 32 Revision History .................................................................................................................................................. 32 Appendix A. Resource Utilization ....................................................................................................... 33 LatticeECP and LatticeEC FPGAs ...................................................................................................................... 34 Ordering Part Number................................................................................................................................ 34 LatticeECP2 and LatticeECP2S FPGAs ............................................................................................................. 34 Ordering Part Number................................................................................................................................ 34 LatticeECP2M and LatticeECP2MS FPGAs ....................................................................................................... 35 Ordering Part Number................................................................................................................................ 35 LatticeECP3 FPGAs............................................................................................................................................ 35 Ordering Part Number................................................................................................................................ 35 LatticeXP FPGAs ................................................................................................................................................ 36 Ordering Part Number................................................................................................................................ 36 LatticeXP2 FPGAs ...
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... The newer standards like IEEE 802.16-2004 require the use of Reed-Solomon codes with dynamically varying block sizes. Lattice’s RS Decoder IP core provides an ideal solution that meets such needs of today’s forward error correction world. This core allows the block size and number of check symbols to be varied dynamically through input ports. Lattice’ ...
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... LUTs Resource Utilization sysMEM EBRs Registers Lattice Implementation Synthesis Design Tool Support Simulation Table 1-3. RS Decoder IP core for LatticeECP2 Devices Quick Facts FPGA Families Supported Core Requirements Minimal Device Needed Targeted Device LUTs Resource Utilization sysMEM EBRs Registers ...
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... LUTs Resource Utilization sysMEM EBRs Registers Lattice Implementation Synthesis Design Tool Support Simulation Table 1-5. RS Decoder IP core for LatticeSCM Devices Quick Facts FPGA Families Supported Core Requirements Minimal Device Needed Targeted Device LUTs Resource Utilization sysMEM EBRs Registers ...
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... LUTs Resource Utilization sysMEM EBRs Registers Lattice Implementation Synthesis Design Tool Support Simulation Table 1-7. RS Decoder IP core for LatticeECP2M Devices Quick Facts FPGA Families Supported Core Requirements Minimal Device Needed Targeted Device LUTs Resource Utilization sysMEM EBRs Registers ...
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... LUTs Resource Utilization sysMEM EBRs Registers Lattice Implementation Synthesis Design Tool Support Simulation Table 1-9. RS Decoder IP core for LatticeECP3 Devices Quick Facts FPGA Families Supported Core Requirements Minimal Device Needed Targeted Device LUTs Resource Utilization sysMEM EBRs Registers ...
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... Lattice Semiconductor – CCSDS – ATSC – IEEE 802.16-2004 WirelessMAN-SCa/OFDM – IEEE 802.16-2004 WirelessMAN-SC • Fully Synchronous • Systematic Decoder • Full Handshaking Capability • Dynamically Variable Block Size • Dynamically Variable Check Symbols • Error, Erasure and Puncturing Modes • ...
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A block diagram of the RS Decoder is shown in Transform, Key Equation Solver, Error Locator, Error Magnitude Corrector, Data Memory and Output Processing blocks. Block Diagram Figure 2-1. RS Decoder Block Diagram Syndrome din Transform Data Memory clk rstn ...
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... Lattice Semiconductor errors is determined, the decoder decides if they are within the range of correction. After determining this, the decoder corrects the errors in the received data. A typical application of space signal processing is shown in Figure 2-2. Figure 2-2. Application of Reed-Solomon Code in a Space Communication System Input Data ...
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... Lattice Semiconductor can be used. If erased symbols are known and the position of the erased symbols can be dynamically indicated using ers, then erasure mode is useful. The symbol correction capability of the decoder increases since the posi- tion of the symbol in error is already known and only the magnitude needs to be computed. Generally erasure sup- port substantially increases the decoder latency and resource utilization ...
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... Lattice Semiconductor 2t S(x)(x) = ¾(x) mod x where: ¾(x) is the Error Evaluator polynomial the number of check symbols introduced in the encoder. The following sections describe the function of each block of the RS Decoder. Syndrome Transform The Syndrome Transform (also called Syndrome Generation) block evaluates the received codeword of the gener- ator polynomial ...
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... Lattice Semiconductor input port numchks, depending on the parameter Variable check symbols. Once block size value, number of check symbols and number of information symbols are known then the core operates in the same way as when block size was constant. Variable Check Symbols This option can be used when there is requirement for variable error correction capability. One example of this type of application is IEEE 802 ...
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... Lattice Semiconductor Table 2-1. Default Field Polynomials Symbol Width Signal Descriptions Table 2-2 shows the definitions of the interface signals available with the RS Decoder IP Core. Table 2-2. Interface Signal Descriptions Port Bits All Configurations 1 clk 1 rstn 1 ibstart din ...
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... Lattice Semiconductor Table 2-2. Interface Signal Descriptions (Continued) Port Bits For Puncturing Mode (when Decoding mode is “Puncturing” and Number of puncture patterns is More than puncsel For Erasure mode 1 ers Optional I/ ddel 1-8 errcnt 1-8 erscnt 1 fail IPUG52_01.6, December 2010 I/O Puncture pattern select signal. The value on this port selects the puncturing pat- tern from the number of predefined patterns for the current block of data ...
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... Lattice Semiconductor Timing Specifications The decoder receives the data in blocks. The assertion of signal ibstart indicates the first symbol of the new block of data at the input of the decoder. The ibstart signal should be asserted only during the first clock cycle of a data block. The ibstart signal should not be re-asserted until the decoder is ready to receive the next block of data as indicated by rfib going high ...
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... Lattice Semiconductor Figure 2-4. Effect of Synchronous Reset on the Output Data from the Decoder clk rstn ce sr rfi rfib ibstart blocksize n numchks c1 puncsel p1 ers din AIn-3 AI0 AI1 AI2 dout ddel outvalid obstart obend errfnd errcnt erscnt fail Figure 2-5 illustrates the effect of clock enable (ce) on the output data from RS Decoder. The decoder ignores all other synchronous inputs and remains in its current state when ce is de-asserted ...
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... Lattice Semiconductor Figure 2-5. Effect of Clock Enable on the Output Data from Decoder clk rstn ce sr rfi rfib ibstart blocksize n numchks c1 puncsel p1 ers din AIn-3 AI0 AI1 AI2 dout ddel outvalid obstart obend errfnd errcnt erscnt fail IPUG52_01.6, December 2010 AIn-2 AIn-1 ...
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The IPexpress™ tool is used to create IP and architectural modules in the Diamond and ispLEVER software. Refer to “IP Core Generation” on page 24 The RS Decoder IP core Configuration GUI allows the user to create a custom configuration ...
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... Lattice Semiconductor RS Decoder Configuration GUI Figure 3-1 shows the contents of the RS Decoder IP core Configuration GUI. Figure 3-1. RS Decoder IP core Configuration GUI Core Configuration Selects between custom and pre-defined standard configurations. ter values for different standard configurations. RS Parameters Wsymb This parameter sets symbol width. ...
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... Lattice Semiconductor Rootspace This parameter sets the root spacing of the generator polynomial. The value of rootspace must satisfy the following equation: GCD(rootspace, 2wsymb- GCD is Greatest Common Divisor. Check Symbols Variable Check Symbols This option allows the number of check symbols to be varied through the port in addition to varying the block size dynamically ...
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... Lattice Semiconductor Optional Ports ce Determines whether the input port ce (clock enable) is present. sr Determines whether the input port sr (synchronous reset) is present. errcnt Determines whether the output port errcnt (error count) is present. ddel Determines whether the output port ddel (delayed data) is present. fail Determines whether the output port fail (decoding failure) is present ...
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... An IP license is required to enable full, unrestricted use of the RS Decoder IP core in a complete, top-level design license that specifies the IP core and device family is required to enable full use of the core in Lattice devices. Instructions on how to obtain licenses for Lattice IP cores are given at: http://www ...
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... Lattice Semiconductor Figure 4-1. IPexpress Tool Dialog Box (Diamond Version) Note that if the IPexpress tool is called from within an existing project, Project Path, Module Output (Design Entry in ispLEVER), Device Family and Part Name default to the specified project parameters. Refer to the IPexpress tool online help for further information. ...
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... Lattice Semiconductor Figure 4-2. Configuration GUI (Diamond Version) IPexpress-Created Files and Top Level Directory Structure When the user clicks the Generate button in the IP Configuration dialog box, the IP core and supporting files are generated in the specified “Project Path” directory. The directory structure of the generated files is shown in Figure 4-3 ...
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... This file provides a module which instantiates the RS Decoder core. This file can be easily <username>_top.[v,vhd] modified for the user's instance of the RS Decoder core. This file is located in the rsdec_eval/<username>_/src/rtl/top/ directory. Created when GUI “Generate” button is pushed, invokes generation, may be run from <username>_generate.tcl command line. < ...
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... Aldec evaluation simulation is provided in \<project_dir>\rsdec_eval\<username>\sim\aldec\scripts. Both Modelsim and Aldec simulation is supported via test bench files provided in \<project_dir>\rsdec_eval\testbench. Models required for sim- ulation are provided in the corresponding \models folder. Users may run the Aldec evaluation simulation by doing the following: 1 ...
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... To use this project file in ispLEVER: 1. Choose File > Open Project. 2. Browse to \<project_dir>\rsdec_eval\<username>\impl\synplify (or precision) in the Open Project dialog box. 3. Select and open <username>.syn. At this point, all of the files needed to support top-level synthesis and imple- mentation will be imported to the project. ...
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... To regenerate an IP core in ispLEVER the IPexpress tool, choose Tools > Regenerate IP/Module the Select a Parameter File dialog box, choose the Lattice Parameter Configuration (.lpc) file of the IP core you wish to regenerate, and click Open. 3. The Select Target Core Version, Design Entry, and Device dialog box shows the current settings for the IP core in the Source Value box ...
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... Receive direct technical support for all Lattice products by calling Lattice Applications from 5:30 a. p.m. Pacific Time. • For USA & Canada: 1-800-LATTICE (528-8423) • For other locations: +1 503 268 8001 In Asia, call Lattice Applications from 8:30 a.m. to 5:30 p.m. Beijing Time (CST), +0800 UTC. Chinese and English language only. • For Asia: +86 21 52989090 E-mail Support • ...
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... Core version 3.0: Full support of IPexpress flow, including LatticeECP/EC, LatticeECP2, LatticeSC, and LatticeXP. 3.1 Updated LatticeECP/EC, LatticeECP2, LatticeXP and LatticeSC appen- dices. Added support for the LatticeECP2M FPGA family. 3.2 Added support for LatticeXP2 FPGA family. 3.3 Added support for LatticeECP3 FPGA family. Added VHDL flow. ...
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... This appendix gives resource utilization information for Lattice FPGAs using the RS Decoder IP core. IPexpress is the Lattice IP configuration utility, and is included as a standard feature of the Diamond and ispLEVER design tools. Details regarding the usage of IPexpress can be found in the IPexpress and Diamond or ispLEVER help system. For more information on the Diamond or ispLEVER design tools, visit the Lattice web site at: ...
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... D-2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP/EC family. Ordering Part Number The Ordering Part Number (OPN) for the RS Decoder core targeting LatticeECP/EC devices is RSDEC-DBLK-E2- U3. LatticeECP2 and LatticeECP2S FPGAs Table A-3. Performance and Resource Utilization ...
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... Lattice D-2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family. Ordering Part Number The Ordering Part Number (OPN) for the RS Decoder core targeting LatticeECP3 devices is RSDEC-DBLK-P3-U3. IPUG52_01.6, December 2010 1 Slices ...
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... D-2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family. Ordering Part Number The Ordering Part Number (OPN) for the RS Decoder core targeting LatticeXP2 devices is RSDEC-DBLK-X2-U3. IPUG52_01.6, December 2010 1 Slices ...
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... Lattice D-2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeSC/M family. Ordering Part Number The Ordering Part Number (OPN) for the RS Decoder core targeting LatticeSC/M devices is RSDEC-DBLK-SC-U3. IPUG52_01.6, December 2010 1 Slices ...