SLATA1GM2PU STEC, SLATA1GM2PU Datasheet

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SLATA1GM2PU

Manufacturer Part Number
SLATA1GM2PU
Description
Memory Cards 1G 3.3-5V
Manufacturer
STEC
Datasheet

Specifications of SLATA1GM2PU

Product Category
Memory Cards
Rohs
yes
Solid-State Memory Card
(No Moving Parts)
Capacity: 128MB - 16GB
ATA-5 Compatible
ATA Transfer modes:
Supports TrueIDE and PC Card
Memory and I/O Modes
Form Factors:
Endurance Guarantee of 2,000,000
Write/Erase Cycles
Card Information Structure (CIS)
Programmed into 256 Bytes of
Internal Memory
PC Card and Socket Services
Release 2.1 or later compatible
5V or 3.3V Power Supply
Commercial and Industrial
Operating Temperature Range
5-Byte Detection, 4-Byte Correction
ECC Engine
10 Year Data Retention
RoHS-6 Compliant
PIO 0-6, MWDMA 0-4
PIO 0-6 only (for applications
that require MWDMA access to
be disabled)
PC Card Type II
128MB to 16GB
ATA PC Card
SLATAxxx(M/G)M1U(I)
General Description and Key Features
STEC’s flash storage adheres to the latest industry compliance and regulatory
standards including UL, FCC, RoHS, and various compliance associations. Each
device incorporates a proprietary state-of-the-art flash memory controller that provides
the greatest flexibility to customer-specific applications while supporting key flash
management features resulting in the industry’s highest reliability and endurance. Key
features include:
STEC’s ATA PC Card is the product of choice in applications requiring high reliability
and high tolerance to shock, vibration, humidity, altitude, ESD, and temperature. The
rugged industrial design combined with industrial temperature (-40°C to 85°C) testing
and adherence to rigid JEDEC JESD22 standards ensures flawless execution in the
harshest environments.
In addition to custom hardware and firmware designs, STEC also offers value-added
services including:
Ordering Information: ATA PC Card
Legend:
Built-in ECC engine detects up to 5-byte and corrects up to 4-byte errors
Sophisticated block management and wear leveling algorithms guarantees
2,000,000 write/erase cycles
Power-down data protection ensures data integrity and errors in case of power loss
Lifecycle management feature allows users to monitor the device’s block
management
Custom labeling and packaging
Custom software imaging and ID strings
Full BOM control and product change notification
Total supply-chain management to ensure continuity of supply
In-field application engineering to help customers through product design-ins
SLATA = STEC standard ATA PC Card part number prefix.
(M/G) = proceeding capacity (xxx) is in Megabytes (M) or Gigabytes (G).
M1 = STEC Mach 1 controller.
U = RoHS-6 compliant lead-free.
Part numbers without (I) = Commercial temperature range (0ºC to 70ºC).
I = Industrial temperature range (-40ºC to +85 ºC).
F = media set to fixed storage for non-removable IDE applications. Use with
operating systems, such as Windows XP, that require storage media to be
identified as a fixed drive before it can be used as a bootable drive. Example:
SLATAxxx(M/G)M1U(I)-F.
P = firmware programmed for PIO Modes 0-6 only for applications requiring
MWDMA access to be disabled. Example: SLATAxxx(M/G)M1U(I)-P
SLATA128MM1U(I)
SLATA256MM1U(I)
SLATA512MM1U(I)
SLATA16GM1U(I)
SLATA1GM1U(I)
SLATA2GM1U(I)
SLATA4GM1U(I)
SLATA8GM1U(I)
Part Number
PC Card Form Factor
Type II
Type II
Type II
Type II
Type II
Type II
Type II
Type II
www.stec-inc.com
128 Mbytes
256 Mbytes
512 Mbytes
16 GBytes
Capacity
2 GBytes
4 GBytes
8 GBytes
1 GByte

Related parts for SLATA1GM2PU

SLATA1GM2PU Summary of contents

Page 1

... Lifecycle management feature allows users to monitor the device’s block management STEC’s ATA PC Card is the product of choice in applications requiring high reliability and high tolerance to shock, vibration, humidity, altitude, ESD, and temperature. The rugged industrial design combined with industrial temperature (-40°C to 85°C) testing and adherence to rigid JEDEC JESD22 standards ensures flawless execution in the harshest environments ...

Page 2

... True IDE Mode Register Access ............................................................................................. 19 3.3.8 True IDE Mode PIO Access .................................................................................................... 20 3.3.9 True IDE Mode Multiword DMA (not used for part numbers with P) ....................................... 22 3.4 PC Card Memory and I/O Modes Power Up to READY and RESET to READY ........................ 23 4.0 Host Access Specification ..............................................................................................24 4.1 Task File Register and Byte/Word/Odd-Byte Mode Mappings ................................................... 24 4 ...

Page 3

... SLATAxxx(M/G)M1U(I) Datasheet 1.0 Product Specifications 1.1 Labeling STEC ATA Cards can be manufactured with standard labeling, or customer-specific, custom labeling. Standard labeling is shown in Figure 1. Figure 1: Standard Labeling 61000-04497-117, April 2008 ATA PC Card 3 ...

Page 4

SLATAxxx(M/G)M1U(I) Datasheet 1.2 Package Dimensions and Pin Locations Table 1 and Figure 2 show the mechanical dimensions of the PC Card Type II. Table 1: Mechanical dimensions PC Card Type II Parameter Length Width Height (including label area) Figure 2: ...

Page 5

SLATAxxx(M/G)M1U(I) Datasheet 1.3 Pin Assignment Pin Signal Name Number 1 GND 2 D03 3 D04 4 D05 5 D06 6 D07 7 -CE1, -CS0 8 A10 9 -OE, -ATASEL 10 N/C 11 A09 12 A08 13 N/C 14 N/C 15 ...

Page 6

... Pin Description Number 62 This output line is always driven to a high state in Memory Mode since a battery is not required for this product. This output line is always driven to a high state in I/O Mode since this product produces no audio. In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in the Master/Slave handshake protocol ...

Page 7

... To enable True IDE Mode, this input should be grounded by the host Memory Mode, this signal is set high when the ATA PC Card is ready to accept a new data transfer operation and held low when the ATA PC Card is busy. The host must provide a pull-up resistor. At power up and at reset, the RDY/-BSY signal is held low (busy) until the ATA PC Card completes its power up or reset function ...

Page 8

... IORDY (True IDE Mode) GND GND (PC Card Memory Mode) GND (PC Card I/O Mode) GND (True IDE Mode) VCC VCC (PC Card Memory Mode) VCC (PC Card I/O Mode) VCC (True IDE Mode) RESET I (PC Card Memory Mode) Pin Description Number The signal must also be active (low) during I/O Cycles when the I/O address is on the bus ...

Page 9

... Pin Number This signal is the same as the PC Card Memory Mode signal. In the True IDE Mode this input pin is the active low hardware reset from the host. 43, 57 -VS1 is grounded so that the card CIS can be read at 3.3 volts. -VS2 is reserved for a secondary voltage and is not connected ...

Page 10

... EN 55024 – ―Information technology equipment – Immunity characteristics – Limits and methods of measurement‖ 1.7.2 RoHS STEC certifies that its products do not contain any of the restricted substances as stated below and are in compliance with RoHS EU directive 2002/95/EC, specifically:  Mercury (Hg)  ...

Page 11

SLATAxxx(M/G)M1U(I) Datasheet 2.0 Environmental Specifications 2.1 Recommended Operating Conditions Table 6: ATA PC Card Recommended Operating Conditions Parameter Commercial Operating Temperature Industrial Operating Temperature VCC voltage 5.0 VCC voltage 3.3 2.2 Reliability Table 7: ATA PC Card Endurance & Data ...

Page 12

SLATAxxx(M/G)M1U(I) Datasheet 3.0 Electrical Specifications 3.1 Absolute Maximum Ratings Table 9: ATA PC Card Absolute Maximum Ratings Parameter Voltage Storage temperature range 3.2 DC Characteristics Measurements at Recommended Operating Conditions unless otherwise specified. Table 10: ATA PC Card DC Characteristics ...

Page 13

... Output Disable Time from -OE Address Setup Time Output Enable Time from -CE Output Enable Time from -OE Data Valid from Address Change Address Hold Time -CE Setup Time -CE Hold Time Figure 3: PC Card Memory Mode Attribute Memory Read Timing Diagram Symbol IEEE Symbol tc(R) tAVAV ta(A) tAVQV ta(CE) ...

Page 14

... Output Disable Time (-WE) Output Disable Time (-OE) Output Enable Time (-WE) Output Enable Time (-OE) Output Enable Setup Time (-WE) Output Enable Hold Time (-WE) -CE Setup Time -CE Hold Time Figure 4: PC Card Memory Mode Attribute Memory Write Timing Diagram Symbol IEEE Symbol tc(W) tAVAV tw(WE) tWLWH tsu(A) tAVWL — ...

Page 15

... Wait Delay Falling from OE tv(WT-OE) (max) Data Setup for Wait Release tv(WT) (max) Wait Width tw(WT) tWTLWTH Time (max) Figure 5: PC Card Memory Mode Common Memory Read Timing Diagram IEEE 250 ns Cycle 120 ns Cycle Symbol Time Mode Time Mode tGLQV 125 60 tGHQZ 100 60 ...

Page 16

... CE Hold following WE th(CE) (min) Wait Delay Falling tv(WT- from WE (max) WE) WE High from Wait tv(WT) Release (min) Wait Width Time tw(WT) (max) Figure 6: PC Card Memory Mode Common Memory Write Timing Diagram 250 ns 120 ns IEEE Cycle Time Cycle Time Symbol Mode Mode tDVWH 80 50 tWMDX ...

Page 17

SLATAxxx(M/G)M1U(I) Datasheet 3.3.5 PC Card I/O Mode Read AC Characteristics Table 15: PC Card I/O Mode Read AC Characteristics Parameter Symbol Data Delay after td(IORD) -IORD (max) Data Hold following -IORD th(IORD) (min) -IORD Width tw(IORD) Time (min) Address Setup ...

Page 18

SLATAxxx(M/G)M1U(I) Datasheet 3.3.6 PC Card I/O Mode Write AC Characteristics Table 16: PC Card I/O Mode Write AC Characteristics Parameter Symbol Data Setup before -IOWR tsu(IOWR) (min) Data Hold following -IOWR th(IOWR) (min) -IOWR Width tw(IOWR) Time (min) Address Setup ...

Page 19

SLATAxxx(M/G)M1U(I) Datasheet 3.3.7 True IDE Mode Register Access Table 17: True IDE Mode Register Access AC Characteristics Parameter Symbol Mode0 Cycle time (min) t0 600 Address valid to -IORD/-IOWR t1 70 (min) setup -IORD/-IOWR pulse width 8bit t2 290 (min) ...

Page 20

SLATAxxx(M/G)M1U(I) Datasheet 3.3.8 True IDE Mode PIO Access Table 18: True IDE Mode PIO Access AC Characteristics Parameter Symbol Mode0 Cycle time (min) t0 600 Address valid to -IORD/-IOWR t1 70 (min) setup -IORD/-IOWR pulse width 8bit t2 290 (min) ...

Page 21

SLATAxxx(M/G)M1U(I) Datasheet Figure 9: True IDE Mode PIO Access Timing Diagram 61000-04497-117, April 2008 ATA PC Card 21 ...

Page 22

SLATAxxx(M/G)M1U(I) Datasheet 3.3.9 True IDE Mode Multiword DMA (not used for part numbers with P) Table 19: True IDE Mode Multiword DMA AC Characteristics Parameter Symbol Cycle time (min) t -IORD/-IOWR Asserted Pulse t (min) -IORD data access (max) t ...

Page 23

... SLATAxxx(M/G)M1U(I) Datasheet 3.4 PC Card Memory and I/O Modes Power Up to READY and RESET to READY Table 20: Power Up to READY and RESET to READY AC Characteristics Parameter Symbol Power up to READY t rdy RESET to READY t rdy Minimum Rec. Reset Width T (reset) w Capacity Min Typ 128MB 0.069 256MB ...

Page 24

... The Card Information Structure (CIS) in Attribute Memory can be accessed by Byte/Word/Odd-byte modes in PC Card Memory Mode. The -REG signal must be asserted when accessing Attribute Memory. The ATA PC Card is mapped to PC Card Memory Mode by the Index bits in the Configuration Option Register. An example of a CIS is listed in 4.3, Card Information Structure (CIS). ...

Page 25

SLATAxxx(M/G)M1U(I) Datasheet 4.3 Card Information Structure (CIS) The ATA PC Card uses a Card Information Structure (CIS) as summarized below: 1. 0000: Code 01, link Tuple CISTPL_DEVICE (01), length 3 (03) at offset 0  Device ...

Page 26

... BVDs not active, WP not active, RdyBsy active  Wait signal support required  Vcc Power Description: Nom V = 5.0 V  Map 2048 bytes of memory to CF Card address 0  Miscellaneous Features: Max Twins 0, -Audio, -ReadOnly, +PowerDown 11. 0048: Code 1B, link Tuple CISTPL_CFTABLE_ENTRY (1B), length 6 (06) at offset 48  ...

Page 27

SLATAxxx(M/G)M1U(I) Datasheet 12. 0050: Code 1B, link Tuple CISTPL_CFTABLE_ENTRY (1B), length10 (0A) at offset 50 10 (0A) at offset 50  Configuration Table Index is 01 (default)  Interface ...

Page 28

SLATAxxx(M/G)M1U(I) Datasheet 16. 007D: Code 1B, link Tuple CISTPL_CFTABLE_ENTRY (1B), length 15 (0F) at offset 7D  Configuration Table Index is 03 (default)  ...

Page 29

... Default number of sectors per track Number of sectors per ATA PC Card (word 7 = MSW, word 8 = LSW) Reserved Serial Number in ASCII (20 characters): STEC proprietary Do not use this word. Before retirement, was buffer type Do not use this word. Before retirement, was buffer size in 512 byte increments # of ECC bytes passed on Read/Write Long commands Firmware revision in ASCII (8 characters): Rev8 ...

Page 30

... Card, and to issue soft resets to it. Also, the Index bits of this register are used to select the PC Card mapping mode that the ATA PC Card uses Card Memory Card Contiguous I/O, 3).PC Card Primary I/O, and 4) PC Card Secondary I/O This register is used for observing the ATA PC Card state. ...

Page 31

SLATAxxx(M/G)M1U(I) Datasheet 5.2 Task File Registers Table 23: ATA PC Card Task File Registers Task File Register The Data Register is a 16-bit read/write register used for transferring data Data Register between the ATA PC Card and the host. This ...

Page 32

SLATAxxx(M/G)M1U(I) Datasheet 6.0 Supported ATA Commands The ATA commands used by the ATA PC Card are listed in Table 24. Refer to ATA PC Card standards for details. Table 24: ATA PC Card Supported ATA Commands Command Set Code Check ...

Page 33

SLATAxxx(M/G)M1U(I) Datasheet Command Set Code Seek 7Xh Set Features EFh Set Multiple Mode C6h Set Sleep Mode E6h or 99h Stand By E2h or 96h Stand By Immediate E0h or 94h Translate Sector 87h Wear Level F5h Write Buffer E8h ...

Page 34

... General Description text updated. -114 11/2/07 Pasting error corrected in CIS (paper error only). -115 11/7/07 Layout updated for consistency and easier editing. Disclaimer notice reformatted with headings. -116 3/7/08 Contact information on last page updated. -117 4/2/08 STEC China address on last page updated. 61000-04497-117, April 2008 ATA PC Card 34 ...

Page 35

... Please contact the STEC™ Inc. sales office to obtain the latest specifications. STEC™ Inc. grants no warranty with respect to this datasheet, neither explicit or implied, and is not liable for direct or indirect damages. Some states do not grant the exclusion of incidental damages and as such this statement may not be valid in such states ...

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