24LC01B/SN Microchip Technology, 24LC01B/SN Datasheet - Page 8

• Manufacturer Part Number: 24LC01B/SN
• Description: IC EEPROM 1KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24LC01B/SN

• Memory Size: 1K (128 x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature: 0°C ~ 70°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 128 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 2.5 V
• Package: 8SOIC N
• Density: 1 Kb
• Maximum Operating Frequency: 0.4 MHz
• Maximum Random Access Time: 900 ns
• Typical Operating Supply Voltage: 3.3|5 V
• Data Retention: 200(Min) Year
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

24AA01/24LC01B
6.0
6.1
Following the Start condition from the master, the
device code (4 bits), the block address (3 bits, “don’t
cares”) and the R/W bit, which is a logic-low, is placed
onto the bus by the master transmitter. This indicates to
the addressed slave receiver that a byte with a word
address will follow after it has generated an Acknowl-
edge bit during the ninth clock cycle. Therefore, the
next byte transmitted by the master is the word address
and will be written into the Address Pointer of the
24XX01. After receiving another Acknowledge signal
from the 24XX01, the master device will transmit the
data word to be written into the addressed memory
location. The 24XX01 acknowledges again and the
master generates a Stop condition. This initiates the
internal write cycle, and, during this time, the 24XX01
will not generate Acknowledge signals (Figure 6-1).
FIGURE 6-1:
DS21711J-page 8
SDA Line
Bus Activity
Master
Bus Activity
WRITE OPERATION
Byte Write
x = “don’t care”
S
S
T
A
R
T
BYTE WRITE
1 0
1 0
Control
Byte
x x x 0
Select
Block
Bits
A
C
K
Address
Word
6.2
The write control byte, word address and first data byte
are transmitted to the 24XX01 in the same way as in a
byte write. However, instead of generating a Stop
condition, the master transmits up to 8 data bytes to the
24XX01, which are temporarily stored in the on-chip
page buffer and will be written into the memory once
the master has transmitted a Stop condition. Upon
receipt of each word, the four lower-order Address
Pointer bits are internally incremented by ‘
higher-order 7 bits of the word address remain
constant. If the master should transmit more than 8
words prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 6-2).
6.3
The WP pin allows the user to write-protect the entire
array (00-7F) when the pin is tied to V
the write protection is disabled.
Note:
Page Write
Write Protection
Page write operations are limited to writing
bytes within a single physical page
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size – 1]. If a
page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
A
C
K
© 2009 Microchip Technology Inc.
Data
CC
. If tied to V
A
C
K
1
P
S
T
O
P
’. The
SS
,