72V851L20TF IDT, 72V851L20TF Datasheet - Page 3

• Manufacturer Part Number: 72V851L20TF
• Description: FIFO
• Manufacturer: IDT

Specifications of 72V851L20TF

• Part # Aliases: IDT72V851L20TF

PIN DESCRIPTIONS
referred to as FIFO A and FIFO B, are identical in every respect. The following
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
D
D
RSA, RSB
WCLKA
WCLKB
WENA1
WENB1
WENA2/LDA
WENB2/LDB
Q
Q
RCLKA
RCLKB
RENA1
RENB1
RENA2
RENB2
OEA
EFA
EFB
PAEA
PAEB
PAFA
PAFB
FFA
FFB
V
GND
The IDT72V801/72V811/72V821/72V831/72V841/72V851's two FIFOs,
A0
B0
CC
Symbol
A0
B0
-D
-D
-Q
-Q
A8
B8
A8
B8
A Data Inputs
B Data Inputs
Reset
Write Clock
Write Enable 1
Write Enable 2/
Load
A Data Outputs
B Data Outputs
Read Clock
Read Enable 1
Read Enable 2
Output Enable
Empty Flag
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Full Flag
Power
Ground
Name
I/O
O When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited. When EFA
O When PAEA (PAEB) is LOW, FIFO A (B) is Almost-Empty based on the offset programmed into the appropriate
O When PAFA (PAFB) is LOW, FIFO A (B) is Almost-Full based on the offset programmed into the appropriate offset
O When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited. When FFA (FFB) is
O 9-bit data outputs from RAM array A.
O 9-bit data outputs from RAM array B.
I
I
I
I
I
I
I
I
I
I
Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write enable(s)
Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1(RENB1) and
9-bit data inputs to RAM array A.
9-bit data inputs to RAM array B.
When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to the first
location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go LOW. After power-
up, a reset of both FIFOs A and B is required before an initial WRITE.
are asserted.
If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only write enable pin that can be
used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO on every LOW-to-HIGH transition
WCLKA (WCLKB). If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW and
WENA2 (WENB2) must be HIGH to write data into the FIFO. Data will not be written into the FIFO if FFA (FFB) is
LOW.
FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB) is HIGH at
reset, this pin operates as a second Write Enable. If WENA2/LDA (WENB2/LDB) is LOW at reset this pin operates
as a control to load and read the programmable flag offsets for its respective array. If the FIFO is configured to have
two write enables, WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into FIFO
A (B). Data will not be written into FIFO A (B) if FFA (FFB) is LOW. If the FIFO is configured to have programmable
flags, LDA (LDB) is held LOW to write or read the programmable flag offsets.
RENA2 (RENB2) are asserted.
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every LOW-to-HIGH
transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every LOW-to-
HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA (EFB) is LOW.
When OEA (OEB) is LOW, outputs D
D
(EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).
offset register. The default offset at reset is Empty+7. PAEA (PAEB) is synchronized to RCLKA (RCLKB).
register. The default offset at reset is Full-7. PAFA (PAFB) is synchronized to WCLKA (WCLKB).
+3.3V power supply pin.
0V ground pin.
HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).
A8
(D
B0
Description
-D
B8
) will be in a high-impedance state.
3
description defines the input and output signals for FIFO A. The corresponding
signal names for FIFO B are provided in parentheses.
A0
-D
A8
(D
TM
B0
-D
B8
) are active. If OEA (OEB) is HIGH, the OEB outputs D
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008
A0
-