74LVC1G32GM-H NXP Semiconductors, 74LVC1G32GM-H Datasheet

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74LVC1G32GM-H

Manufacturer Part Number
74LVC1G32GM-H
Description
Logic Gates 3.3V 2-CH ANALOG M/DEM
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC1G32GM-H

Product Category
Logic Gates
Rohs
yes
Product
OR
Logic Family
LVC
Number Of Gates
1
Number Of Lines (input / Output)
2 / 1
High Level Output Current
- 32 mA
Low Level Output Current
32 mA
Propagation Delay Time
2.5 ns
Supply Voltage - Max
5.5 V
Supply Voltage - Min
1.65 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOT-886
Minimum Operating Temperature
- 40 C
Number Of Input Lines
2
Number Of Output Lines
1
Factory Pack Quantity
5000
Part # Aliases
74LVC1G32GM,132
1. General description
2. Features and benefits
The 74LVC1G32 provides one 2-input OR function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall
time.
This device is fully specified for partial power-down applications using I
The I
the device when it is powered down.
74LVC1G32
Single 2-input OR gate
Rev. 10 — 4 September 2012
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
ESD protection:
24 mA output drive (V
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
OFF
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
circuitry disables the output, preventing the damaging backflow current through
CC
= 3.0 V)
Product data sheet
OFF
.

Related parts for 74LVC1G32GM-H

74LVC1G32GM-H Summary of contents

Page 1

Single 2-input OR gate Rev. 10 — 4 September 2012 1. General description The 74LVC1G32 provides one 2-input OR function. Inputs can be driven from either 3 devices. This feature allows the use of these ...

Page 2

... Marking Table 2. Marking Type number 74LVC1G32GW 74LVC1G32GV 74LVC1G32GM 74LVC1G32GF 74LVC1G32GN 74LVC1G32GS 74LVC1G32GX [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74LVC1G32 GND 3 001aab640 Fig 4. Pin configuration SOT353-1 and SOT753 74LVC1G32 GND 3 Transparent top view Fig 6. Pin configuration SOT891, SOT1115 and SOT1202 6.2 Pin description Table 3. Pin description Symbol Pin TSSOP5 and X2SON5 XSON6 ...

Page 4

... NXP Semiconductors 7. Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol ...

Page 5

... NXP Semiconductors 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/V input transition rise and fall rate V 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). ...

Page 6

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage GND current 5 power-off OFF CC leakage current I supply current GND 1. 5 I additional per pin ...

Page 7

... NXP Semiconductors 12. AC waveforms Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 8. The input output Y propagation delays Table 9. Measurement points Supply voltage 1. 2.7 V 2 3 5.5 V ...

Page 8

... NXP Semiconductors Table 10. Test data Supply voltage Input 2.7 V 2 3.6 V 2 74LVC1G32 Product data sheet Load  2  2  2  2  2 All information provided in this document is subject to legal disclaimers. ...

Page 9

... NXP Semiconductors 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1. DIMENSIONS (mm are the original dimensions UNIT max. 0.1 1.0 mm 1.1 0.15 0 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE ...

Page 10

... NXP Semiconductors Plastic surface-mounted package; 5 leads DIMENSIONS (mm are the original dimensions UNIT 0.100 0.40 1.1 0.26 mm 0.013 0.25 0.9 0.10 OUTLINE VERSION IEC SOT753 Fig 11. Package outline SOT753 (SC-74A) 74LVC1G32 Product data sheet scale ...

Page 11

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. (2) terminal 1 index area Dimensions (mm are the original dimensions) (1) Unit max 0.5 0.04 0.25 1.50 mm nom 0.20 1.45 min 0.17 1.40 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version ...

Page 12

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 13. Package outline SOT891 (XSON6) ...

Page 13

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1115 Fig 14. Package outline SOT1115 (XSON6) ...

Page 14

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version IEC SOT1202 Fig 15. Package outline SOT1202 (XSON6) ...

Page 15

... NXP Semiconductors X2SON5: plastic thermal enhanced extremely thin small outline package; no leads; 5 terminals; body 0.8 x 0 terminal 1 index area e 1 terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.128 0.85 mm nom 0.80 min 0.040 0.75 Note 1. Dimension A is including plating thickness. 2. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 16

... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date 74LVC1G32 v.10 20120904 • Modifications: Package outline drawing of SOT1226 74LVC1G32 v ...

Page 17

... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 18

... Product data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

Page 19

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Package outline ...

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