25LC160-I/SN Microchip Technology, 25LC160-I/SN Datasheet - Page 8

• Manufacturer Part Number: 25LC160-I/SN
• Description: IC EEPROM 16KBIT 2MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 25LC160-I/SN

• Memory Size: 16K (2K x 8)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 2MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 2K X 8 / 1K X 16
• Ic Interface Type: SPI
• Clock Frequency: 2MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25LCXXX
3.0
3.1
The 25LCXXX are Mid-Density Serial EEPROMs
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular micro-
controller families, including Microchip’s PIC
controllers. It may also interface with microcontrollers
that do not have a built-in SPI port by using discrete I/
O lines programmed properly in firmware to match the
SPI protocol.
The 25LCXXX contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25LCXXX in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
TABLE 3-1:
DS22131C-page 8
Instruction Name
WRITE
READ
WRDI
WREN
RDSR
WRSR
FUNCTIONAL DESCRIPTION
Principles of Operation
INSTRUCTION SET
Instruction Format
0000 0011
0000 0010
0000 0100
0000 0110
0000 0101
0000 0001
®
micro-
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
Reset the write enable latch (disable write operations)
Set the write enable latch (enable write operations)
Read STATUS register
Write STATUS register
Preliminary
Block Diagram
HOLD
SCK
WP
SO
CS
SI
I/O Control
Register
STATUS
Logic
Description
V
V
CC
SS
Memory
Control
© 2009 Microchip Technology Inc.
Logic
Dec
X
Sense Amp.
R/W Control
Y Decoder
HV Generator
Page Latches
EEPROM
Array