24LC65/P Microchip Technology, 24LC65/P Datasheet - Page 5

• Manufacturer Part Number: 24LC65/P
• Description: IC EEPROM 64KBIT 400KHZ 8DIP
• Manufacturer: Microchip Technology

Specifications of 24LC65/P

• Memory Size: 64K (8K x 8)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 6.0 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Memory Configuration: 8K X 8
• Ic Interface Type: I2C
• Clock Frequency: 400kHz
• Supply Voltage Range: 2.5V To 6V
• Memory Case Style: DIP
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.0
The 24XX65 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the serial clock
(SCL), controls the bus access and generates the Start
and Stop conditions, while the 24XX65 works as slave.
Both master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.
3.0
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Both data and clock lines remain high.
3.2
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
FIGURE 3-1:
© 2008 Microchip Technology Inc.
SDA
is not busy.
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
SCL
FUNCTIONAL DESCRIPTION
BUS CHARACTERISTICS
Bus not Busy (A)
Start Data Transfer (B)
(A)
Condition
Start
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Acknowledge
Address or
Valid
(D)
To Change
24AA65/24LC65/24C65
Allowed
Data
3.3
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.4
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
3.5
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX65) must leave the data line high to enable
the master to generate the Stop condition.
Note:
Stop Data Transfer (C)
Data Valid (D)
Acknowledge
The 24XX65 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
(D)
DS21073K-page 5
Condition
Stop
(C)
(A)