CAT1161WI-25-G ON Semiconductor, CAT1161WI-25-G Datasheet
CAT1161WI-25-G
Specifications of CAT1161WI-25-G
Related parts for CAT1161WI-25-G
CAT1161WI-25-G Summary of contents
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... CAT1161, CAT1162 Supervisory Circuits with Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer (16K) Description The CAT1161 complete memory and supervisory solution for microcontroller−based systems. A serial EEPROM memory (16K) with hardware memory write protection, a system power supervisor with brown out protection and a watchdog timer are integrated together in low power CMOS technology ...
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Table 1. RESET THRESHOLD OPTION Part Dash Minimum Number Threshold −45 4.50 −42 4.25 −30 3.00 −28 2.85 −25 2.55 BLOCK DIAGRAM EXTERNAL LOAD D OUT ACK V CC WORDADDRESS GND BUFFERS START/STOP SDA LOGIC XDEC CONTROL WP LOGIC RESET ...
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Table 2. ABSOLUTE MAXIMUM RATINGS Parameters Temperature Under Bias Storage Temperature Voltage on any Pin with Respect to Ground (Note 1) V with Respect to Ground CC Package Power Dissipation Capability (T Lead Soldering Temperature (10 sec) Output Short Circuit ...
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Table 6. AC CHARACTERISTICS 6.0 V unless otherwise specified. Output Load is TTL Gate and 100 pF. CC Symbol F Clock Frequency SCL T (Note 1) Noise Suppression Time Constant at SCL, SDA Inputs 1 ...
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WP: WRITE PROTECT If the pin is tied to V the entire memory array becomes CC Write Protected (READ only). When the pin is tied to GND or left floating normal read/write operations are allowed to the device. RESET/RESET: RESET ...
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Hardware Data Protection The CAT1161/2 is designed with the following hardware data protection features to provide a high degree of data integrity. 1. The CAT1161/2 features a WP pin. When the WP pin is tied high the entire memory array ...
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The CAT1161/2 supports the I C Bus data transmission protocol. This Inter−Integrated Circuit Bus protocol defines any device that sends data to the bus transmitter and any device receiving data receiver. The transfer ...
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Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends a ...
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The READ operation for the CAT1161/2 is initiated in the same manner as the write operation with one exception, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Selective/Random READ and Sequential READ. Immediate/Current Address ...
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BUS ACTIVITY: SLAVE R MASTER ADDRESS T SDA LINE S Figure 10. Selective Read Timing BUS ACTIVITY: SLAVE MASTER ADDRESS DATA n SDA LINE Figure 11. Sequential Read Timing BYTE SLAVE ...
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... CAT1161LI−25−G 2.55 V − 2.70 V CAT1161WI−45−GT3 4.50 V − 4.75 V CAT1161WI−42−GT3 4.25 V − 4.50 V CAT1161WI−30−GT3 3.00 V − 3.15 V CAT1161WI−28−GT3 2.85 V − 3.00 V CAT1161WI−25−GT3 2.55 V − 2.70 V CAT1162LI−45−G 4.50 V − 4.75 V CAT1162LI−42−G 4.25 V − 4.50 V CAT1162LI−30−G 3.00 V − 3.15 V CAT1162LI−28−G 2.85 V − 3.00 V CAT1162LI−25−G 2.55 V − ...
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PIN # 1 IDENTIFICATION D TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A SYMBOL ...
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