CAT1161WI-25-G ON Semiconductor, CAT1161WI-25-G Datasheet - Page 8

• Manufacturer Part Number: CAT1161WI-25-G
• Description: Supervisory Circuits CPU w/16K
• Manufacturer: ON Semiconductor

Specifications of CAT1161WI-25-G

• Product Category: Supervisory Circuits
• Rohs: yes
• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Undervoltage Threshold: 2.55 V
• Overvoltage Threshold: 2.7 V
• Output Type: Active High, Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 270 ms
• Supply Voltage - Max: 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Wide
• Chip Enable Signals: No
• Maximum Power Dissipation: 1000 mW
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Supply Current (typ): 3000 uA
• Supply Voltage - Min: 2.7 V

Byte Write
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends a 8−bit address
that is to be written into the address pointers of the
CAT1161/2. After receiving another acknowledge from the
Slave, the Master device transmits the data to be written into
the
acknowledges once more and the Master generates the
STOP condition. At this time, the device begins an internal
programming cycle to non−volatile memory. While the
cycle is in progress, the device will not respond to any
request from the Master device.
Acknowledge Polling
the typical write cycle time. Once the stop condition is issued
to indicate the end of the host’s write operation, the
CAT1161/2 initiates the internal write cycle. ACK polling
can be initiated immediately. This involves issuing the start
against inadvertent memory array programming. If the WP
pin is tied to V
becomes read only. The CAT1161/2 will accept both slave
In the Byte Write mode, the Master device sends the
Disabling of the inputs can be used to take advantage of
The Write Protection feature allows the user to protect
addressed
BUS ACTIVITY:
SDA LINE
MASTER
CC
, the entire memory array is protected and
memory
S
BUS ACTIVITY:
R
S
T
A
T
location.
SDA LINE
ADDRESS
MASTER
SLAVE
The
S
S
A
R
T
T
A
C
K
ADDRESS (n)
ADDRESS
Figure 8. Page Write Timing
Figure 7. Byte Write Timing
CAT1161/2
SLAVE
WRITE OPERATIONS
WRITE PROTECTION
BYTE
http://onsemi.com
C
A
K
A
C
K
8
ADDRESS
Page Write
write cycle, using the Page Write operation. The page write
operation is initiated in the same manner as the byte write
operation, however instead of terminating after the initial
byte is transmitted, the Master is allowed to send up to 15
additional bytes. After each byte has been transmitted, the
CAT1161/2 will respond with an acknowledge and
internally increment the lower order address bits by one. The
high order bits remain unchanged.
the STOP condition, the address counter ‘wraps around,’
and previously transmitted data will be overwritten.
has been sent by the Master, the internal programming cycle
begins. At this point, all received data is written to the
CAT1161/2 in a single write cycle.
condition followed by the slave address for a write
operation. If the CAT1161/2 is still busy with the write
operation, no ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can then
proceed with the next read or write operation.
and byte addresses, but the memory location accessed is
protected from programming by the device’s failure to send
an acknowledge after the first byte of data is received.
BYTE
DATA n
The CAT1161/2 writes up to 16 bytes of data in a single
If the Master transmits more than 16 bytes before sending
When all 16 bytes are received, and the STOP condition
A
C
K
A
C
K
DATA n+1
DATA
C
A
K
C
A
K
P
O
S
T
P
DATA n+15
C
A
K
O
S
T
P
P