7024S55JI8 IDT, 7024S55JI8 Datasheet - Page 11

• Manufacturer Part Number: 7024S55JI8
• Description: SRAM
• Manufacturer: IDT

Specifications of 7024S55JI8

• Part # Aliases: IDT7024S55JI8

Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing
NOTES:
1. R/W or CE or UB & LB = V
2. A write occurs during the overlap (t
3. t
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW = V
6. Timing depends on which enable signal is asserted last, CE, R/W, UB, or LB.
7.
8.
9. To access RAM, CE = V
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
CE or SEM
CE or SEM
ADDRESS
ADDRESS
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
DATA
UB or LB
(Figure 2).
placed on the bus for the required t
specified t
met for either condition.
UB or LB
WR
If OE = V
DATA
This parameter is guaranted by device characterization, but is not production tested. Transition is measured 0mV steady state with the Output Test Load
DATA
is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH = V
R/W
R/W
OUT
OE
IN
IN
WP .
IL
(9)
(9)
(9)
(9)
during R/W controlled write cycle, the write pulse width must be the larger of t
IL
, UB or LB = V
IL
IH
transition occurs simultaneously with or after the R/W = V
during all address transitions.
t
AS
t
DW
AS
EW
(6)
. If OE = V
(6)
or t
IL
WP
, and SEM = V
(4)
) of a UB or LB = V
IH
during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
t
WZ
IH
. To access Semaphore, CE = V
(7)
t
t
AW
AW
t
t
WC
WC
IL
and a CE = V
t
t
WP
EW
(2)
(2)
6.42
11
IL
IL
and a R/W = V
to the end-of-write cycle.
t
t
IL
DW
DW
transition, the outputs remain in the High-impedance state.
Military, Industrial and Commercial Temperature Ranges
IH
WP
or UB & LB = V
for (t
IL
t
WR
WZ
for memory array writing cycle.
(3)
+ t
DW
t
t
t
DH
DH
WR
) to allow the I/O drivers to turn off and data to be
IH
t
, and SEM = V
OW
(3)
t
HZ
IL
. t
(7)
EW
must be
(4)
(1,5,8)
2740 drw 10
2740 drw 09
(1,5)