7024S55JI8 IDT, 7024S55JI8 Datasheet - Page 14

• Manufacturer Part Number: 7024S55JI8
• Description: SRAM
• Manufacturer: IDT

Specifications of 7024S55JI8

• Part # Aliases: IDT7024S55JI8

NOTES:
1. To ensure that the earlier of the two ports wins. t
2. CE
3. OE = V
4. If M/S = V
5. All timing is the same for both left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY
NOTES:
1. t
2. BUSY is asserted on port "B" Blocking R/W
3. t
Timing Waveform of Write with Port-to-Port Read and BUSY
DATA
IDT7024S/L
High-Speed 4K x 16 Dual-Port Static RAM
WH
DATA
WB
ADDR
ADDR
BUSY
L
must be met for both BUSY input (slave) and output (master).
is only for the 'Slave' Version.
= CE
R/W
OUT "B"
IN "A"
IL
R
for the reading port.
"A"
"A"
"B"
"B"
IL
= V
(slave) then BUSY is an input BUSY
IL
.
t
APS
(1)
BUSY
R/W
R/W
"A"
"B"
"B"
"B"
, until BUSY
"A"
APS
= V
is ignored for M/S = V
IL
"B"
and BUSY
t
WB
goes HIGH.
(3)
t
"B"
BAA
= don't care, for this example.
MATCH
IL
6.42
14
t
(SLAVE).
t
WC
WP
(2)
Military, Industrial and Commercial Temperature Ranges
t
WP
t
DW
MATCH
t
WDD
VALID
t
WH
(1)
2740 drw 14
t
DDD
(3)
(2,4,5)
,
t
BDA
t
DH
(M/S = V
2740 drw 13
t
BDD
VALID
IH
)